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Tanner Swett (talk | contribs) →Clock polarity and phase: Change "is outputted" to "is output" |
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The SPI [[digital timing diagram|timing diagram]] shown is further described below:
* CPOL represents the polarity of the clock. Polarities can be converted with a simple [[inverter (logic gate)|inverter]].
** SCLK{{Subscript|1=CPOL=0}} is a clock
** SCLK{{Subscript|1=CPOL=1}} is a clock
* CPHA represents the [[Phase (waves)|phase]] of each data bit's transmission cycle relative to SCLK.
** For CPHA=0:
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