C-element: Difference between revisions

Revision as of 00:02, 18 July 2024

Revision as of 00:04, 18 July 2024

Line 41:

[[Image:Dual-rail C-element.png|thumb|upright=1.5|An STG of dual-rail C-element with 00 transit and its circuit realized only on NAND2 as a particular case of<ref name="Varsh85" /> considered by V.B. Marakhovsky.]]

[[Image:David cell graph.png|thumb|upright=1.7|David cell (a) and its fast implementations: gate-level (b) and transistor-level (c)<ref>A. Bystrov, A. Yakovlev, [http://citeseer.ist.psu.edu/viewdoc/download;jsessionid=9FB34454CF987BC939FF0377A3EAD0BB?doi=10.1.1.16.5667&rep=rep1&type=pdf Asynchronous circuit synthesis by direct mapping: Interfacing to environment]. Technical Report, CS Department, University of Newcastle upon Tyne, October 2001.</ref>]]

There is a number of different single-output circuits of C-element built on logic gates.<ref>B. S. Tsirlin, [https://patentimages.storage.googleapis.com/bd/d8/4b/81b12c002a0615/SU1096759A1.pdf "H flip-flop"], USSR author's certificate SU1096759, Jun. 7, 1984.</ref><ref>B. S. Tsirlin, [https://patentimages.storage.googleapis.com/b1/bf/92/42303ee73cf5ac/SU1162019A1.pdf "Multiple input H flip-flop"], USSR author's certificate SU1162019, Jun. 15, 1985.</ref> In particular, the so-called Maevsky's implementation <ref name="Kuwa94">M. Kuwako, T. Nanya, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=656283 "Timing-reliability evaluation of asynchronous circuits based on different delay models"], IEEE Int. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp. 22–31.</ref><ref name="Brz95">J.{{cite A.book Brzozowski,| K. Raahemifar, [httpchapter-url=https://ieeexplore.ieee.org/xpldocument/articleDetails.jsp?arnumber514652 | doi=10.1109/WCADM.1995.514652 "| chapter=Testing C-elements is not elementary"], | title=Proceedings Second Working Conference on Asynchronous Design Methodologies (ASYNC)| date=1995, pp| last1=Brzozowski | first1=J.A. 150–159| last2=Raahemifar | first2=K. | pages=150–159 | isbn=0-8186-7098-3 }}</ref><ref>P. A. Beerel, J. R. Burch, T. H. Meng, [https://link.springer.com/article/10.1023/A:1008666605437 "Checking combinational equivalence of speed-independent circuits"], Formal Methods in System Design, vol. 13, no. 1, 1998, pp. 37–85.</ref> is a semimodular, but non-distributive (OR-causal) circuit loosely based on.<ref>V. I. Varshavsky, O. V. Maevsky, Yu. V. Mamrukov, B. S. Tsirlin, [https://patentimages.storage.googleapis.com/fb/81/d2/fa3a9d86aa6917/SU1081801A1.pdf "H flip-flop"], USSR author's certificate SU1081801, Mar. 23, 1984</ref> The NAND3 gate in this circuit can be replaced by two NAND2 gates. Note that Maevsky's C-element is actually a Join element, whose input signals cannot switch twice.<ref name="Kuwa94"/> Yet another circuit with OR-causality, which operates as a Join element.<ref>G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, [https://patentimages.storage.googleapis.com/41/1a/f8/394838c3c7d619/SU1432733A1.pdf "H-flip-flop"], USSR author's certificate SU1432733, Oct. 23, 1988.</ref> A realization of C-element on two-input gates only has been proposed by Tsirlin <ref>B. S. Tsirlin, [https://patentimages.storage.googleapis.com/d0/78/f9/43bc147866ddb5/SU1324106A1.pdf "H-flip-flop"], USSR author's certificate SU1324106, Jul. 15, 1987.</ref> and then synthesized by Starodoubtsev et al. using Taxogram language<ref name="Star04">N. A. Starodoubtsev, S. A. Bystrov, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1354042&matchBoolean=true&searchWithin%5B%5D=%22Last+Name%22%3Astarodoubtsev&newsearch=true "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits"], IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521–524.</ref> This circuit coincides with that attributed to Bartky

,<ref name="Kim71" /><ref name="Kuwa94" /> and can operate without the input latch.

Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.<ref>[https://ieeexplore.ieee.org/document/4244956 M. Courvoisier and P. Azema, "Asynchronous sequential machines with request/acknowledge operating mode," IEE Electronics Letters, Vol. 10, no. 1, pp.8-10, 1974.]</ref> Its fast transistor-level implementation is used in the semistatic C-element proposed.<ref>S. M. Fairbanks, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=US&NR=6281707B1&KC=B1&FT=D&ND=3&date=20010828&DB=EPODOC&locale=en_EP "Two-stage Muller C-element"], United States Patent US6281707, Aug. 28, 2001.</ref> Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.<ref>A. Morgenshtein, M. Moreinis, R. Ginosar, [http://webee.technion.ac.il/~ran/papers/Async-GDI-circuits-Nov02.pdf "Asynchronous gate-diffusion-input (GDI) circuits"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 847–856, 2004.</ref> Yet another version of the C-element built on two [[RS latch#Simple set-reset latches|SR-latches]] has been synthesized by Murphy<ref>J. P. Murphy, [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6317230 "Design of latch-based C-element"], Electronics Letters, vol. 48, no. 19, 2012, pp. 1190–1191.</ref> using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example.<ref>V. A. Maksimov and Ya. Ya. Petrichkovich [https://yandex.ru/patents/doc/SU1164867A1_19850630 "RS flip-flop,"] USSR author's certificate SU1164867, Jun. 30, 1985.</ref> Some speed-independent approaches<ref>P. Beerel and T. H.-Y. Meng. [http://dl.acm.org/citation.cfm?id=304171 "Automatic gate-level synthesis of speed-independent circuits"], IEEE/ACM Int. Conference on Computer-Aided Design (ICCAD) 1992, pp. 581–587.</ref><ref>A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, [http://dl.acm.org/citation.cfm?id=196275 "Basic gate implementation of speed-independent circuits"], ACM Design Automation Conference (DAC) 1994, pp. 56–62.</ref> assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.<ref>A. V. Yakovlev, A. M. Koelmans, A. Semenov, D. J. Kinniment, [http://www.sciencedirect.com/science/article/pii/S0167926096000107 "Modelling, analysis and synthesis of asynchronous control circuits using Petri nets"], Integration, the VLSI Journal, vol. 21, no. 3, pp. 143—170, 1996.</ref>