Random-access memory: Difference between revisions

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CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. [[Intel Corporation|Intel]] summarized these causes in a 2005 document.<ref>{{Cite web |title= Platform 2015: Intel Processor and Platform Evolution for the Next Decade |date= March 2, 2005 |url= http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |url-status= live |archive-url= https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |archive-date= April 27, 2011 }}</ref>

<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor [[Leakage (electronics)|leakage current]] increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called [[Vonvon Neumann architecture#Vonvon Neumann bottleneck|Vonvon Neumann bottleneck]]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, [[RC time constant#Delay|resistance-capacitance]] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>

The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"<ref>{{Cite conference |first1=Vikas |last1=Agarwal |first2=M. S. |last2=Hrishikesh |first3=Stephen W. |last3=Keckler |first4=Doug |last4=Burger |title=Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures |url=http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf |conference=27th Annual International Symposium on Computer Architecture |conference-url=https://dl.acm.org/citation.cfm?id=339647 |book-title=Proceedings of the 27th Annual International Symposium on Computer Architecture |___location=Vancouver, BC |date=June 10–14, 2000 |access-date=14 July 2018}}</ref> which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.