Memory controller: Difference between revisions

Revision as of 19:47, 3 September 2024

Revision as of 14:03, 10 October 2024

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ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to choose which memory scrambling standard to use (ASUS or Intel) or whether to turn the feature off entirely.{{cn|date=September 2024}}<!--[[User:Kvng/RTH]]-->

== Variants ==

=== Double data rate memory ===

[[Double data rate]] (DDR) memory controllers are used to drive [[DDR SDRAM]], where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers ,{{Citation needed| reason= Why would it be significantly more complicated - provide reliable source if possible | date=April 2018}}, but they allow for twice the data to be transferred without increasing the memory cell's clock rate or bus width.

=== Multichannel memory ===

{{Main|Multi-channel memory architecture}}

Multichannel memory memory controllers are memory controllers where the DRAM devices are separated on toonto multiple different buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM cell would be the ideal solution, adding more channels isincreases verycomplexity difficult due to wire count,and cost.<!--[[line capacitanceUser:Kvng/RTH]], and the need for parallel access lines to have identical lengths.-->

=== Fully buffered memory ===