Random-access memory: Difference between revisions

Revision as of 13:45, 8 September 2024

Revision as of 18:31, 8 September 2024

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[[File:Electronic Memory.jpg|thumb| A 64 bit memory chip die, the SP95 Phase 2 Buffer Memory produced at IBM mid 60s, versus [[Magnetic-core memory|memory core iron rings]]]]

[[File:Swissbit 2GB PC2-5300U-555.jpg|right|thumb|Example of [[read/write memory|writable]] [[volatile memory|volatile]] random-access memory: Synchronous [[Dynamic RAM]] [[DIMM|modules]], primarily used as main memory in [[personal computers]], [[workstation]]s, and [[Server (computing)|server]]s.]]

[[File:Random Access Memory HyperX.jpg|thumb|8GB [[DDR3]] [[RAM]] stick with a white [[Heat sink|heatsink]]]]

'''Random-access memory''' ('''RAM'''; {{IPAc-en|r|æ|m}}) is a form of [[Computer memory|electronic computer memory]] that can be read and changed in any order, typically used to store working [[Data (computing)|data]] and [[machine code]].<ref>{{cite web |title=RAM |url=https://dictionary.cambridge.org/dictionary/english/ram |website=[[Cambridge English Dictionary]] |access-date=11 July 2019}}</ref><ref>{{cite web |title=RAM |url=https://www.oxfordlearnersdictionaries.com/definition/american_english/ram_2 |website=[[Oxford Advanced Learner's Dictionary]] |access-date=11 July 2019}}</ref> A [[Random access|random-access]] memory device allows data items to be [[read (computer)|read]] or written in almost the same amount of time irrespective of the physical ___location of data inside the memory, in contrast with other direct-access data storage media (such as [[hard disk]]s and [[Magnetic tape data storage|magnetic tape]]), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.

In today's technology, random-access memory takes the form of [[integrated circuit]] (IC) chips with [[MOSFET|MOS]] (metal–oxide–semiconductor) [[Memory cell (computing)|memory cells]]. RAM is normally associated with [[Volatile memory|volatile]] types of memory where stored information is lost if power is removed. The two main types of volatile random-access [[semiconductor memory]] are [[static random-access memory]] (SRAM) and [[dynamic random-access memory]] (DRAM).

Non-volatile RAM has also been developed<ref>{{cite magazine|last=Gallagher|first=Sean|title=Memory that never forgets: non-volatile DIMMs hit the market|url=https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|magazine=[[Ars Technica]]|url-status=live|archive-url=https://web.archive.org/web/20170708073138/https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|archive-date=July 8, 2017|date=April 4, 2013}}</ref> and other types of [[Non-volatile memory|non-volatile memories]] allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of [[read-only memory|ROM]] and [[NOR flash memory]].

The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their [[IBM System/360|System/360 Model 95]] computer, and [[Toshiba]] used discrete DRAM memory cells for its 180-bit Toscal BC-1411 [[electronic calculator]], both based on [[bipolar transistor]]s. While it offered higher speeds than [[magnetic-core memory]], bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref> Memory based on MOS transistors was developed in the late 1960s and was the basis for all early commercial semiconductor memory. The first commercial DRAM IC chip, the 1K [[Intel 1103]], was introduced in October 1970. [[Synchronous dynamic random-access memory]] (SDRAM) later debuted with the [[Samsung Electronics|Samsung]] KM48SL2000 chip in 1992.

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[[Dynamic random-access memory]] (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away. [[Toshiba]]'s Toscal BC-1411 [[electronic calculator]], which was introduced in 1965,<ref>[http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator Toscal BC-1411 calculator]. {{webarchive|url=https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator |date=2017-07-29 }}, [[Science Museum, London]].</ref><ref name="bc-spec"/><ref name="bc"/> used a form of capacitive bipolar DRAM, storing 180-bit data on discrete [[Memory cell (computing)|memory cells]], consisting of [[germanium]] bipolar transistors and capacitors.<ref name="bc-spec"/><ref name="bc"/> While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref>

[[File:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|right|CMOS 1-[[megabit]] (Mbit) DRAM chip, one of the last models developed by [[Carl Zeiss AG|VEB Carl Zeiss Jena]] in 1989]]

MOS technology is the basis for modern DRAM. In 1966, Dr. [[Robert H. Dennard]] at the [[IBM Thomas J. Watson Research Center]] was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building [[capacitor]]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="Robert Dennard"/> The first commercial DRAM IC chip was the [[Intel 1103]], which was [[Semiconductor manufacturing process|manufactured]] on an [[10 μm process|8{{nbsp}}μm]] MOS process with a capacity of 1{{nbsp}}[[Kilobit|kbit]], and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=The Invention of the Intel 1103 |access-date=2015-07-11 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead }}</ref>

[[Synchronous dynamic random-access memory]] (SDRAM) was developed by [[Samsung Electronics]]. The first commercial SDRAM chip was the Samsung KM48SL2000, which had a capacity of 16{{nbsp}}[[Megabit|Mbit]].<ref name="electronic-design">{{cite journal |title=Electronic Design |journal=[[Electronic Design]] |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref> It was introduced by [[Samsung]] in 1992,<ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref> and mass-produced in 1993.<ref name="electronic-design"/> The first commercial [[DDR SDRAM]] ([[double data rate]] SDRAM) memory chip was Samsung's 64{{nbsp}}Mbit DDR SDRAM chip, released in June 1998.<ref>{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref> [[GDDR]] (graphics DDR) is a form of DDR [[SGRAM]] (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mbit memory chip in 1998.<ref>{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref>

==Types==

The two widely used forms of modern RAM are [[static random access memory|static RAM]] (SRAM) and [[dynamic random-access memory|dynamic RAM]] (DRAM). In SRAM, a [[Bit|bit of data]] is stored using the state of a six-[[transistor]] [[Memory cell (computing)|memory cell]], typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as [[CPU cache|cache memory for the CPU]]. DRAM stores a bit of data using a transistor and [[capacitor]] pair (typically a MOSFET and [[MOS capacitor]], respectively),<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=[[Wiley (publisher)|Wiley]] |isbn=0-471-33372-7 |page=214 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref> which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.

Both static and dynamic RAM are considered ''volatile'', as their state is lost or reset when power is removed from the system. By contrast, [[read-only memory]] (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as [[EEPROM]] and [[NOR flash]]) share properties of both ROM and RAM, enabling data to [[Persistence (computer science)|persist]] without power and to be updated without requiring special equipment. [[ECC memory]] (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using [[parity bit]]s or [[Error detection and correction#Error-correcting code|error correction codes]].

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The memory cell is the fundamental building block of [[computer memory]]. The memory cell is an [[electronic circuit]] that stores one [[bit]] of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

In SRAM, the memory cell is a type of [[flip-flop (electronics)|flip-flop]] circuit, usually implemented using [[field effect transistor|FET]]s. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density.

A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.

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Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.

CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. [[Intel Corporation|Intel]] summarized these causes in a 2005 document.<ref>{{Cite web |title= Platform 2015: Intel Processor and Platform Evolution for the Next Decade |date= March 2, 2005 |url= http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |url-status= live |archive-url= https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |archive-date= April 27, 2011 }}</ref>

<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor [[Leakage (electronics)|leakage current]] increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called [[von Neumann architecture#von Neumann bottleneck|von Neumann bottleneck]]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, [[RC time constant#Delay|resistance-capacitance]] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>

The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"<ref>{{Cite conference |first1=Vikas |last1=Agarwal |first2=M. S. |last2=Hrishikesh |first3=Stephen W. |last3=Keckler |first4=Doug |last4=Burger |title=Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures |url=http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf |conference=27th Annual International Symposium on Computer Architecture |conference-url=https://dl.acm.org/citation.cfm?id=339647 |book-title=Proceedings of the 27th Annual International Symposium on Computer Architecture |___location=Vancouver, BC |date=June 10–14, 2000 |access-date=14 July 2018}}</ref> which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.

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A different concept is the processor-memory performance gap, which can be addressed by [[Three-dimensional integrated circuit|3D integrated circuits]] that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.<ref>{{cite book |page=790 |url=https://books.google.com/books?id=1PgYS7zDCM8C&q=processor-memory+performance+gap&pg=PA790 |access-date=March 31, 2014 |title=Nanoelectronics and Information Technology |author=Rainer Waser |publisher=John Wiley & Sons |year=2012 |url-status=live |archive-url=https://web.archive.org/web/20160801114150/https://books.google.com/books?id=1PgYS7zDCM8C&pg=PA790&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CDYQ6AEwAg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn = 9783527409273|author-link = Rainer Waser}}</ref> Memory subsystem design requires a focus on the gap, which is widening over time.<ref>{{cite book |url=https://books.google.com/books?id=0IY7LW5J4JgC&q=processor-memory+performance+gap&pg=PA109 |page=109 |access-date=March 31, 2014 |title=Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings |author=Chris Jesshope and Colin Egan |publisher=Springer |date=2006 |url-status=live |archive-url=https://web.archive.org/web/20160801135254/https://books.google.com/books?id=0IY7LW5J4JgC&pg=PA109&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CEkQ6AEwBg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540400561 }}</ref> The main method of bridging the gap is the use of [[Cache (computing)|caches]]; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.<ref>{{cite book |url=https://books.google.com/books?id=7i9Z69lrYBoC&q=processor-memory+performance+gap&pg=PA90 |pages=90–91 |access-date=March 31, 2014 |title=Multiprocessor Systems-on-chips |author=Ahmed Amine Jerraya and Wayne Wolf |publisher=Morgan Kaufmann |year=2005 |url-status=live |archive-url=https://web.archive.org/web/20160801105357/https://books.google.com/books?id=7i9Z69lrYBoC&pg=PA90&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CFMQ6AEwCA#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9780123852519 }}</ref> There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.<ref>{{cite book |url=https://books.google.com/books?id=f0pJYJQMlmoC&q=processor-memory+performance+gap&pg=PA529 |page=529 |access-date=March 31, 2014 |title=Experimental and Efficient Algorithms: Third International Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3 |author=Celso C. Ribeiro and Simone L. Martins |publisher=Springer |year=2004 |url-status=live |archive-url=https://web.archive.org/web/20160801092734/https://books.google.com/books?id=f0pJYJQMlmoC&pg=PA529&dq=processor-memory+performance+gap&hl=en&sa=X&ei=1eM5U7veEaTx2QXM2oDYCw&ved=0CCwQ6AEwADgU#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540220671 }}</ref>

[[Solid-state drive|Solid-state hard drives]] have continued to increase in speed, from ~400&nbsp;Mbit/s via [[Serial ATA|SATA3]] in 2012 up to ~3&nbsp;GB/s via [[NVM Express|NVMe]]/[[PCI Express|PCIe]] in 2018, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane [[DDR4 SDRAM|DDR4]] 3200 capable of 25&nbsp;GB/s, and modern [[GDDR SDRAM|GDDR]] even faster. Fast, cheap, [[Non-volatile memory|non-volatile]] solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in [[server farm]]s - 1 [[terabyte]] of SSD storage can be had for $200, while 1&nbsp;TB of RAM would cost thousands of dollars.<ref>{{Cite web|url=https://www.minitool.com/news/ssd-prices-fall.html|title=SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!|date=2018-09-03|website=MiniTool|language=en-us|access-date=2019-03-28}}</ref><ref>{{Cite web|url=https://www.digitaltrends.com/computing/ram-prices-are-increasing-until-third-quarter-2017/|title=If you're buying or upgrading your PC, expect to pay more for RAM|last=Coppock|first=Mark|date=31 January 2017|website=www.digitaltrends.com|access-date=2019-03-28}}</ref>

==Timeline==

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|1987

|{{?}}

|1 [[megabit|Mbit]]

|{{?}}

|MOSFET

Line 587:

|MK4816

|16 kbit

|[[Pseudostatic RAM|PSRAM]]

|[[Mostek]]

|{{?}}

Line 642:

|{{sort|1984|January 5, 1984}}

|{{?}}

|8 [[Megabit|Mbit]]

|DRAM

|[[Hitachi]]

Line 661:

|-

|NTT

|[[800 nanometer|800 nm]]

|CMOS

|53&nbsp;mm²

Line 669:

|TMS4161

|64 kbit

|[[Dual-ported RAM|DPRAM]] ([[Video RAM (dual-ported DRAM)|VRAM]])

|[[Texas Instruments]]

|{{?}}

Line 746:

|DRAM

|Hitachi, NEC

|[[250 nanometer|250 nm]]

|CMOS

|{{?}}

Line 762:

| rowspan="2" |{{sort|1995|January 9, 1995}}

| rowspan="2" |{{?}}

| rowspan="2" |1 [[Gigabit|Gbit]]

| rowspan="2" |DRAM

|NEC