IBM System/360 Model 20: Difference between revisions

Revision as of 18:22, 14 September 2024

Revision as of 18:23, 14 September 2024

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==Architecture==

The Model 20 was available with six memory sizes: 4, 8, 12, 16, 24 and 32&nbsp;KB. As in other models of System/360 memory is byte-addressable.<ref name=FuncChar />{{rp|p.1}} It has eight 16-bit [[Processor register|general purpose registers]] numbered R8 through R15 which can be used in computations as base [[Addressing mode#Base plus offset, and variations|register]]s. All of memory is also directly addressable through a feature, called direct addressing, that combines the twelve -bit displacement and the low-order bits of what would normally be the base register field of the instruction (R0-R7) to form a combined fifteen bit address.<ref name=FuncChar />{{rp|p.4}} No storage protection is provided, except for the low 144 bytes of "protected area".

The instruction set is a subset of System/360 consisting of 37 instructions instead of 143,<ref name=FuncChar />{{rp|pp.7–25}}<ref>{{cite book|last=Pugh|first=Emerson W.|title=Building IBM: Shaping an Industry and Its Technology|year=1995|publisher=MIT Press|isbn=0-262-16147-8|url=http://mitpress.mit.edu/catalog/item/default.asp?ttype=2&tid=7339|access-date=2012-10-15|archive-date=2012-05-05|archive-url=https://web.archive.org/web/20120505165349/http://mitpress.mit.edu/catalog/item/default.asp?ttype=2&tid=7339|url-status=dead}}</ref>{{rp|p.384}} with some incompatible instructions, such as a BASR (Branch And Store Register) rather than BALR (Branch And Link Register).