Segger Microcontroller Systems: Difference between revisions

Revision as of 04:51, 15 October 2024

Revision as of 04:54, 15 October 2024

Line 25:

|+ <big>J-Trace & J-Link Models</big><ref>[http://www.segger.com/jlink-model-overview.html J-Link Model Overview; segger.com]</ref>

|-

! Model !! Host<br/>[[USB#Version history|USB]]<br />[[USB#Release_versions|speed]] !! Host<br/>[[Ethernet physical layer|Ethernet]]<br />speed !! Host<br/>[[Wi-Fi]]<br />&nbsp; !! Debug<br />[[Pin header|connector]]<br />(pin pitch) !! Trace<br/>[[Pin header|connector]]<br />&nbsp; !! Target<br/>[[volt]]age<br />&nbsp; !! Target max<br />interface<br />speed !! Target max<br />download<br />speed !! Target<br />[[Virtual COM port|VCOM]]<br />[[Universal asynchronous receiver-transmitter|UART]] !! Software<br />features<br />&nbsp; !! ImagePhoto<br />&nbsp;<br />&nbsp;

|-

| style="text-align:left" | J-Trace PRO Cortex-A/R/M || {{yes|3.0 SS}} || {{yes|1 Gbit/s}} || None || 20-pin (0.1") || {{yes|19-pin 0.05"}} || 1.2V to 5V || {{yes|50&nbsp;[[MHz]]}} || {{yes|4 MByte/s}} || 2 pins || All || [[File:J-Trace Cortex-ARM 1349x1466 230627.png|95px]]