Compressed instruction set: Difference between revisions

Revision as of 20:27, 11 November 2024

Revision as of 21:56, 12 November 2024

Line 18:

One notable, and particularly early, exception amongst RISC designs is the [[IBM 801]] architecture which maintains five instruction formats: two utilising a 16-bit instruction length, and three utilising a 32-bit instruction length.<ref name="ibm_801_system_architecture">{{ cite book | url=http://bitsavers.org/pdf/ibm/system801/System_801_Principles_of_Operation_Jan76.pdf | title=System 801 Principles of Operation | publisher=International Business Machines | date=16 January 1976 | access-date=11 November 2024 }}</ref>{{rp|pages=10}} For instructions requiring less space, such as shift instructions employing only register operands, the shorter 16-bit instruction formats are used.<ref name="ibm_801_system_architecture"/>{{rp|pages=51–58}}

In the 1980s, when the RISC concept was first emerging, thisincreased program size was a common point of complaint. As the instructions took up more room, the system would have to spend more time reading instructions from memory. It was suggested these extra accesses might actually slow the program down. Extensive [[benchmarking]] eventually demonstrated RISC was faster in almost all cases, and this argument faded. However, there are cases where memory use remains a concern regardless of performance, and that is in small systems and embedded applications. Even in the early 2000s, the price of [[DRAM]] was enough that cost-sensitive devices had limited memory. It was for this market that [[Hitachi]] developed the [[SuperH]] design.<ref>{{cite web |url=http://resource.renesas.com/lib/eng/e_learnig/sh4/02/index.html |title=Effects of 16-bit instructions |website=Renesas}}</ref>

In the earlier SuperH designs, SH-1 through SH-4, instructions always take up 16 bits. The resulting instruction set has real-world limitations; for instance, it can only perform two-operand math of the form {{code|A {{=}} A + B}}, whereas most processors of the era used the three-operand format, {{code|A {{=}} B + C}}. By removing one operand, four bits are removed from the instruction (there are 16 registers, needing 4 bits), although this is at the cost of making math code somewhat more complex to write. For the markets targeted by the SuperH, this was an easy tradeoff to make. A significant advantage of the 16-bit format is that the [[instruction cache]] now holds twice as many instructions for any given amount of [[Static random-access memory|SRAM]]. This allows the system to perform at higher speeds, although some of that might be mitigated by the use of additional instructions needed to perform operations that might be performed by a single 3-operand instruction.{{sfn|SuperH|1996}}