Dynamic random-access memory: Difference between revisions

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'''Page mode DRAM''' is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row was opened by holding {{overline|RAS}} low, the row could be kept open, and multiple reads or writes could be performed to any of the columns in the row. Each column access was initiated by presenting a column address and asserting {{overline|CAS}} and presenting a column address. For reads, after a delay (''t''_CAC), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address.<ref name="Kenner 13">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=13}}</ref>

Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement were called '''fast page mode DRAMs''' ('''FPM DRAMs'''). In page mode DRAM, the chip did not capture the column address until {{overline|CAS}} was asserted, before theso column addressaccess time (until data out was suppliedvalid) began when {{overline|CAS}} was asserted. In FPM DRAM, the column address could be supplied while {{overline|CAS}} was still deasserted., The column address propagated throughand the main column addressaccess datatime path,(''t''_AA) butbegan didas notsoon outputas datathe onaddress thewas datastable. pins untilThe {{overline|CAS}} signal was asserted.only Priorneeded to {{overline|CAS}}enable beingthe asserted,output (the data out pins were held at high-Z. FPMwhile DRAM{{overline|CAS}} reducedwas deasserted), so time from {{overline|CAS}} assertion to data valid (''t''_CAC) latencywas greatly reduced.<ref name="Kenner 14">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=14}}</ref> Fast page mode DRAM was introduced in 1986 and was used with the [[Intel 80486]].

''Static column'' is a variant of fast page mode in which the column address does not need to be stored inlatched, but rather, the address inputs may be changed with {{overline|CAS}} held low, and the data output will be updated accordingly a few nanoseconds later.<ref name="Kenner 14" />

''Nibble mode'' is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of {{overline|CAS}}. The difference from normal page mode is that the address inputs are not used for the second through fourth {{overline|CAS}} edges; theybut are generated internally starting with the address supplied for the first {{overline|CAS}} edge.<ref name="Kenner 14" /> The predictable addresses let the chip prepare the data internally and respond very quickly to the subsequent {{overline|CAS}} pulses.

====Extended data out DRAM====