<!-- This section is linked from [[Page mode RAM]] -->
<!-- Change the above redirects if you change the title to this section (section links in redirects are case sensitive) -->
'''Page mode DRAM''' is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row wasis opened by holding {{overline|RAS}} low, the row couldcan be kept open, and multiple reads or writes couldcan be performed to any of the columns in the row. Each column access wasis initiated by presenting a column address and asserting {{overline|CAS}}. For reads, after a delay (''t''<sub>CAC</sub>), valid data would appearappears on the data out pins, which wereare held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would beis presented along with the column address.<ref name="Kenner 13">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=13}}</ref>
Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement wereare called '''fast page mode DRAMs''' ('''FPM DRAMs'''). In page mode DRAM, the chip diddoes not capture the column address until {{overline|CAS}} wasis asserted, so column access time (until data out was valid) beganbegins when {{overline|CAS}} wasis asserted. In FPM DRAM, the column address couldcan be supplied while {{overline|CAS}} wasis still deasserted, and the main column access time (''t''<sub>AA</sub>) beganbegins as soon as the address wasis stable. The {{overline|CAS}} signal wasis only needed to enable the output (the data out pins were held at high-Z while {{overline|CAS}} was deasserted), so time from {{overline|CAS}} assertion to data valid (''t''<sub>CAC</sub>) wasis greatly reduced.<ref name="Kenner 14">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=14}}</ref> Fast page mode DRAM was introduced in 1986 and was used with the [[Intel 80486]].
''Static column'' is a variant of fast page mode in which the column address does not need to be latched, but rather the address inputs may be changed with {{overline|CAS}} held low, and the data output will be updated accordingly a few nanoseconds later.<ref name="Kenner 14" />
