Intel 5-level paging: Difference between revisions

Revision as of 13:32, 10 December 2024

Revision as of 13:33, 10 December 2024

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{{Use dmy dates|date=August 2018}}

'''Intel 5-level paging''', referred to simply as ''5-level paging'' in [[Intel]] documents, is a processor extension for the [[x86-64]] line of processors.<ref name="intel-white-paper">{{Cite web|url=https://www.intel.com/content/www/us/en/content-details/671442/5-level-paging-and-5-level-ept-white-paper.html|title=5-Level Paging and 5-Level EPT|publisher=Intel Corporation|date=May 2017}}</ref>{{Rp|11}} It extends the size of [[virtual address]]es from 48&nbsp;bits to 57&nbsp;bits by adding an additional level to x86-64's [[Page table#Multilevel page tables|multilevel page tables]], increasing the addressable [[virtual memory]] from 256&nbsp;[[tebibyte|TiB]] to 128&nbsp;[[pebibyte|PBPiB]]. The extension was first implemented in the [[Ice Lake (microprocessor)|Ice Lake]] processors.<ref name="anandtech-13699">{{Cite web|url=https://www.anandtech.com/show/13699/intel-architecture-day-2018-core-future-hybrid-x86/2|title=Sunny Cove Microarchitecture: A Peek At the Back End|work=Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86|last=Cutress|first=Ian|access-date=2019-10-15}}</ref>

== Technology ==

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[[File:Page Tables (5 levels).svg|thumb|A diagram of five levels of paging]]

5-level paging adds another 9 bit page table descriptor, making it possible to use bits&nbsp;0 through&nbsp;56. This multiplies the address space by 512 and increases the limit to 128&nbsp;PBPiB.

With 5-level paging enabled, bits&nbsp;57 through&nbsp;63 must be copies of bit&nbsp;56.<ref name="intel-white-paper" />{{Rp|17}} This is the same as with 4-level paging, where the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit.