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Line 5: == Technology == [[File:X86 Paging 64bit.svg\|thumb\|right\|555px\|4-level paging of the 64-bit mode]] In the 4-level paging scheme (previously known as [[IA-32e]] paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit [[X86-64#Page table structure\|page table entry]] in a 512-entry page table for each of the four paging levels. This makes it possible to use bits 0 through 47 in the virtual address, for a total of 256 TiB.<ref name="x86-software-developers-manual" />{{Rp\|page=4{{hyp}}2}}

Intel 5-level paging: Difference between revisions