Bus (computing): Difference between revisions

Revision as of 00:22, 11 December 2024

Revision as of 14:37, 7 January 2025

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Accessing an individual byte frequently requires reading or writing the full bus width (a [[Word (data type)|word]]) at once. In these instances the least significant bits of the address bus may not even be implemented - it is instead the responsibility of the controlling device to isolate the individual byte required from the complete word transmitted. This is the case, for instance, with the [[VESA Local Bus]] which lacks the two least significant bits, limiting this bus to [[Data structure alignment|aligned]] 32-bit transfers.

Historically, there were also some examples of computers whichthat were only able to address words -- {{snd}}[[word machine]]s.

==Memory bus==

{{Unreferenced section|date=June 2023}}

The ''memory bus'' is the bus whichthat connects the [[main memory]] to the [[memory controller]] in [[computer systems]]. Originally, general-purpose buses like [[VMEbus]] and the [[S-100 bus]] were used, but to reduce [[latency (engineering)|latency]], modern memory buses are designed to connect directly to DRAM chips, and thus are designeddefined by chip standards bodies such as [[JEDEC]]. Examples are the various generations of [[SDRAM]], and serial point-to-point buses like [[SLDRAM]] and [[RDRAM]]. An exception is the [[Fully Buffered DIMM]] which, despite being carefully designed to minimize the effect, has been criticized for its higher latency.

==Implementation details==