Successive-approximation ADC: Difference between revisions

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==Charge-redistribution successive-approximation ADC==

[[File:ChargeScalingDAC.png|right|thumb|300px|Charge-scaling DAC]]

One of the most common SAR ADC implementations uses a charge-scaling [[Digital-to-analog converter|DAC]] consisting of an array of individually-switched [[capacitors]] sized in [[powers of two]] (and withan aadditional duplicate of the smallest capacitor), for a total of {{math|''N''+1}} capacitors for {{math|''N''}} bits. Thus if the largest capacitance is {{math|''C''}}, then the array's total capacitance is {{math|2''C''}}. The amountswitched ofcapacitor array acts as both the sample-and-hold element and the DAC. Redistributing their [[Electric charge|charge]] uponwill eachadjust capacitortheir net voltage, which is usedfeed withinto the negative input of a comparator (whose positive input is always grounded) to perform the binary search using the following steps:<ref>{{Cite web |last=Kugelstadt |first=Thomas |date=2000 |title=The operation of the SAR-ADC based on charge redistribution |url=https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf |url-status=live |archive-url=https://web.archive.org/web/20241227083825/https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf |archive-date=2024-12-27 |access-date=2024-12-28 |website=[[Texas Instruments]]}}</ref><ref>{{Cite web |date=2020 |title=Operation of a SAR-ADC Based on Charge Redistribution |url=https://www.renesas.com/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100 |url-status=live |archive-url=https://web.archive.org/web/20241015132842/https://www.renesas.com/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100 |archive-date=2024-10-15 |access-date=2024-12-28 |website=[[Renesas Electronics]]}}</ref>

[[File:CAPadc.png|thumb|3 bit capacitive ADC, using {{math|1=''V''_ref = 5V}}. The bottom left transient simulation uses {{math|''V''_in ≅ 3.5V}} or about {{math|.7}} of {{math|''V''_ref}}, resulting in an answer of {{math|{{frac|5|8}}}} (101 in binary), representing {{math|3.125V}} or {{math|0.625}} of {{math|''V''_ref}}. The remaining fractional voltage is left on the array.|300x300px]]

[[File:CAPadc.png|thumb|3 bits simulation of a capacitive ADC]]

# Discharge: The capacitors are discharged. to(Note, thedischarging to comparator's offset voltage. Thiswill automatically providesprovide offset cancellation.)

# Sampling: The capacitors are switched to the input signal {{math|''V''_in}}. TheAfter a brief sampling period, the capacitors nowwill hold a charge equal to their respective capacitance times {{math|''V''_in}} (and minus the offset voltage upon each of them), so the array holds a total charge of {{math|2''C''·''V''_in}}.

# Hold: The capacitors are then switched to ground. This provides the comparator's negative input with a voltage of {{math|−''V''_in}}.

# TheConversion: the actual conversion process proceeds with the following steps in each iteration, starting with the largest capacitor as the test capacitor for the MSB, and then proceeding in order with each next smaller capacitor for each next bit of lower significance:

## Redistribution: The current test capacitor is switched to {{math|''V''_ref}}. The test capacitor forms a charge divider with the remainder of the array whose ratio depends on the capacitor's relative size. In the first iteration, the ratio is {{math|1:1}}, so the comparator's negative input becomes {{math|−''V''_in + {{frac|''V''_ref|2}}}}. On the {{math|''i''^th}} iteration, the ratio will be {{math|1:2^''i''−1}}, so the {{math|''i''^th}} iteration of this redistribution step effectively adds {{math|{{frac|''V''_ref|2^''i''}}}} to the voltage.

## Comparison: The comparison is performedcomparator's tooutput determinedetermines the bit's value for to the current test capacitor. In the first iteration, if {{math|''V''_in}} is greater than {{frac|''V''_ref|2}}, then the comparator will output a digital 1 and otherwise output a digital 0.

## Update Switch: A digital 1 results in that capacitor being switched ground for subsequent iterations, while a digital 0 results in that capacitor remaining left connected to {{math|''V''_ref}}. Thus, each {{math|''i''^th}} iteration may or may not add {{math|{{frac|''V''_ref|2^''i''}}}} to the comparator's negative input voltage. For instance, the voltage at the end of the first iteration will be {{math|−''V''_in + MSB·{{frac|''V''_ref|2}}}}.

# End Of Conversion: After all capacitors are tested in the same manner, the comparator's negative input voltage will have converged as close as possible (given the resolution of the DAC) to the comparator's offset voltage.

== See also ==