Revision as of 17:48, 28 December 2024 edit Vincent Lefèvre (talk \| contribs) Extended confirmed users 5,215 edits →IEEE 754 quadruple-precision binary floating-point format: binary128: added some details; use standard terminology. ← Previous edit		Revision as of 17:51, 28 December 2024 edit undo Vincent Lefèvre (talk \| contribs) Extended confirmed users 5,215 edits removed inaccurate and unclear paragraph (and this concerned only internals) Next edit →
Line 167: Quadruple-precision (128-bit) hardware implementation should not be confused with "128-bit FPUs" that implement [[Single instruction, multiple data\|SIMD]] instructions, such as [[Streaming SIMD Extensions]] or [[AltiVec]], which refers to 128-bit [[Vector processor\|vectors]] of four 32-bit single-precision or two 64-bit double-precision values that are operated on simultaneously. ~~== Add. info and curiosities ==~~ The IEEE 754 standard allows two different views / decodings for the numbers, one described above with a fractional understanding of the significand and a bias of 16383 for the exponent, the other understanding the significand as binary integer, 2^112 times larger, and in turn the bias for the significand 112 larger, 16495, which produces smaller effective exponents and by that the same final result. The fractional view is common for binaryxxx datatypes, while the integral is for decimalxxx datatypes. Section 3.3 "Sets of floating-point data" in 2019 ver. of the standard. == See also ==

Quadruple-precision floating-point format: Difference between revisions