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Quadruple-precision (128-bit) hardware implementation should not be confused with "128-bit FPUs" that implement [[Single instruction, multiple data|SIMD]] instructions, such as [[Streaming SIMD Extensions]] or [[AltiVec]], which refers to 128-bit [[Vector processor|vectors]] of four 32-bit single-precision or two 64-bit double-precision values that are operated on simultaneously.
== Additional info and curiosities ==
The IEEE 754 standard allows two different views / decodings for the numbers, see Section 3.3 "Sets of floating-point data" in 2019 ver. of the standard. One as described above with a fractional understanding of the significand and a bias of 16383 for the exponent, the other understanding the significand as binary integer, 2^112 times larger, and in turn the bias for the exponent 112 larger, 16495, which produces smaller effective exponents and by that the same final result. The fractional view is common for binaryxxx datatypes, while the integral is for decimalxxx datatypes.
== See also ==
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