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{{Redirect|DRAM||Dram (disambiguation){{!}}Dram}}
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[[Image:MT4C1024-HD.jpg|upright=1.4|thumb|A [[Die (integrated circuit)|die]] photograph of the [[Micron Technology]] MT4C1024 DRAM [[integrated circuit]] (1994). It has a capacity of 1 [[megabit]] equivalent to <math>2^{20}</math>bits or {{nowrap|128 [[KiB]].}}<ref name=mt4acid>{{cite web |access-date=2016-04-02 |date=2012-11-15 |title=How to "open" microchip and what's inside? : ZeptoBars |url=http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside |quote=Micron MT4C1024 — 1 mebibit (220 bit) dynamic ram. Widely used in 286 and 386-era computers, early 90s. Die size - 8662x3969μm. |url-status=live |archive-url=https://web.archive.org/web/20160314015357/http://zeptobars.com/en/read/how-to-open-microchip-asic-what-inside |archive-date=2016-03-14 }}</ref>]]
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The [[cryptanalysis|cryptanalytic]] machine code-named ''Aquarius'' used at [[Bletchley Park]] during [[World War II]] incorporated a hard-wired dynamic memory. Paper tape was read and the characters on it "were remembered in a dynamic store." The store used a large bank of capacitors, which were either charged or not, a charged capacitor representing cross (1) and an uncharged capacitor dot (0). Since the charge gradually leaked away, a periodic pulse was applied to top up those still charged (hence the term 'dynamic')".<ref>{{cite book |first1=B. Jack |last1=Copeland |title=Colossus: The secrets of Bletchley Park's code-breaking computers |url=https://books.google.com/books?id=YiiQDwAAQBAJ&pg=PA301 |date=2010 |publisher=Oxford University Press |isbn=978-0-19-157366-8 |page=301}}</ref>
In November 1965, [[Toshiba]] introduced a bipolar dynamic RAM for its [[electronic calculator]] Toscal BC-1411.<ref name="toscal">{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Spec Sheet for Toshiba "TOSCAL" BC-1411|website=www.oldcalculatormuseum.com|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref>
The earliest forms of DRAM mentioned above used [[bipolar transistors]]. While it offered improved performance over [[magnetic-core memory]], bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref> Capacitors had also been used for earlier memory schemes, such as the drum of the [[Atanasoff–Berry Computer]], the [[Williams tube]] and the [[Selectron tube]].
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The first DRAM with multiplexed row and column [[address bus|address lines]] was the [[Mostek]] MK4096 4 Kbit DRAM designed by Robert Proebsting and introduced in 1973. This addressing scheme uses the same address pins to receive the low half and the high half of the address of the memory cell being referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of address lines required, which enabled it to fit into packages with fewer pins, a cost advantage that grew with every jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16 Kbit density, the cost advantage increased; the 16 Kbit Mostek MK4116 DRAM,<ref>{{cite web |first=Ken |last=Shirriff |title=Reverse-engineering the classic MK4116 16-kilobit DRAM chip |date=November 2020 |url=http://www.righto.com/2020/11/reverse-engineering-classic-mk4116-16.html}}</ref><ref>{{cite web |first=Robert |last=Proebsting |interviewer=Hendrie, Gardner |title=Oral History of Robert Proebsting |date=14 September 2005 |publisher=Computer History Museum |id=X3274.2006 |url=https://www.cs.utexas.edu/~hunt/class/2016-spring/cs350c/documents/Robert-Proebsting.pdf}}</ref> introduced in 1976, achieved greater than 75% worldwide DRAM market share. However, as density increased to 64 Kbit in the early 1980s, Mostek and other US manufacturers were overtaken by Japanese DRAM manufacturers, which dominated the US and worldwide markets during the 1980s and 1990s.
Early in 1985, [[Gordon Moore]] decided to withdraw Intel from producing DRAM.<ref>
By 1986, many, but not all, United States chip makers had stopped making DRAMs.<ref>{{cite book |first1=William R. |last1=Nester |title=American Industrial Policy: Free or Managed Markets? |url=https://books.google.com/books?id=hCi_DAAAQBAJ |date=2016 |publisher=Springer |isbn=978-1-349-25568-9 |page=115}}
</ref> Micron Technology and Texas Instruments continued to produce them commercially, and IBM produced them for internal use.
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|newspaper=New York Times
|date=3 August 1985}}
<
{{cite news |first1=Donald |last1=Woutat.
|url=https://www.latimes.com/archives/la-xpm-1985-12-04-fi-625-story.html |title=6 Japan Chip Makers Cited for Dumping
|newspaper=Los Angeles Times
|date=4 November 1985}}
<
{{cite news |url=https://www.latimes.com/archives/la-xpm-1986-03-14-fi-20761-story.html |title=More Japan Firms Accused: U.S. Contends 5 Companies Dumped Chips
|newspaper=Los Angeles Times
|date=1986}}
<
{{cite news |first1=David E. |last1=Sanger
|url=https://www.nytimes.com/1987/11/03/business/japanese-chip-dumping-has-ended-us-finds.html |title=Japanese Chip Dumping Has Ended, U.S. Finds
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|url=http://edition.cnn.com/2001/TECH/industry/10/25/chip.dumping.idg/ |title=Japanese chip makers say they suspect dumping by Korean firms |publisher=CNN
|date=2001}}
<
{{cite news |url=https://www.itworld.com/article/2794396/japanese-chip-makers-suspect-dumping-by-korean-firms.html |title=Japanese chip makers suspect dumping by Korean firms |newspaper=ITWorld
|date=2001}}
<
{{cite web |url=https://www.eetimes.com/dram-pricing-investigation-in-japan-targets-hynix-samsung/ |title=DRAM pricing investigation in Japan targets Hynix, Samsung
|date=2001 |publisher=EETimes }}
<
{{cite web |url=https://phys.org/news/2006-01-korean-dram-japan.html |title=Korean DRAM finds itself shut out of Japan |publisher=Phys.org
|date=2006 }}
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The row address of the row that will be refreshed next is maintained by external logic or a [[Counter (digital)|counter]] within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.
Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.<ref>
===Memory timing===
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