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The row address of the row that will be refreshed next is maintained by external logic or a [[Counter (digital)|counter]] within the DRAM. A system that provides the row address (and the refresh command) does so to have greater control over when to refresh and which row to refresh. This is done to minimize conflicts with memory accesses, since such a system has both knowledge of the memory access patterns and the refresh requirements of the DRAM. When the row address is supplied by a counter within the DRAM, the system relinquishes control over which row is refreshed and only provides the refresh command. Some modern DRAMs are capable of self-refresh; no external logic is required to instruct the DRAM to refresh or to provide a row address.
Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.<ref>{{cite journal |url=https://www.usenix.org/legacy/event/sec08/tech/full_papers/halderman/halderman_html/ |title=Lest We Remember: Cold Boot Attacks on Encryption Keys |archive-url=https://web.archive.org/web/20150105103510/https://www.usenix.org/legacy/event/sec08/tech/full_papers/halderman/halderman_html/ |archive-date=2015-01-05 |author=Halderman et al |journal =USENIX Security |date=2008}}</ref>
===Memory timing===
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