Depletion-load NMOS logic: Difference between revisions

Revision as of 12:04, 12 January 2025

Revision as of 20:03, 6 April 2025

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[[File:Nmos depletion and.svg|right|thumb|A depletion-load NMOS [[NAND gate]]]]

In [[integrated circuit]]s, '''depletion-load NMOS''' is a form of digital [[logic family]] that uses only a single power supply voltage, unlike earlier [[NMOS logic|NMOS]] (n-type [[metal-oxide semiconductor]]) logic families that needed more than one differentmultiple power supply voltagevoltages. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many [[microprocessor]]s and other logic elements.

[[Depletion and enhancement modes|Depletion-mode]] n-type [[MOSFET]]s as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better [[current source]] approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).