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IBM System/360 architecture: Difference between revisions

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| align=center valign=top | 0-7
| valign=top style="align:left;" | {{anchor|System_Mask}}System Mask
| valign=top | bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,{{#tag:ref|On a processor that complies with the S/360 architecture, the highest channel number is 6. Eleven bits are sufficient to identify the cuu, and seven bits are sufficient to provide masking of I/O interruptions. However, on a 360/67-2 with two 2846 channel controllers, channels are numbered 0-6 and 8-14;<ref name=GA27-2719/>{{rp|page=15}} similarly, the 360/195 had an extended channel feature<ref name=A22-6943/>{{rp|page=21}} but numbered the channels 0 through 13.<ref name=A22-6943/>{{rp|page=25}} I/O interruptions for Channel Controller 1 on the 360/67-2 were masked using control registers, and the 360/195 used bit 7 (Channel 6) of the System Mask as a summary mask bit for channels 6 and up. ''Interruptions from More than Seven Channels''{{sfn|PoOps}}{{rp|pagep=121.4}} describes the summary masking for additional channels, but other text in Principles of Operation still refers to a limit of 7 channels. Standard software supported channels 0-F.|group=NB|name=ChanNum}} bit 7: enable External interruptions (timer, interrupt key, and external signal{{sfn|PoOps}}{{rp|page=71}}
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| align=center valign=top | 8-11
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| align=center valign=top | 16-31
| valign=top | {{anchor|Interruption_Code}}Interruption Code
| code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loaded{{sfn|PoOps}}{{rp|pagep=77}}
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| align=center valign=top | 32-33
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| align=center valign=top | 36-39
| valign=top | {{anchor|Program_Mask}}Program Mask
| bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance{{sfn|PoOps}}{{rp|pagep=71}}
|-
| align=center valign=top|40-63
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! align=right valign=top | Priority
|-
| [[#Input/Output interruption|Input/Output]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=78–7978-79}} || 38&nbsp;&nbsp;&nbsp;56 || 78&nbsp;&nbsp;120 || align=right | 4
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| [[#Program interruption|Program]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=79–80.1}} || 28&nbsp;&nbsp;&nbsp;40 || 68&nbsp;104 || align=right | 2
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| [[#Supervisor Call interruption|Supervisor Call]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=80.1–81}} || 20&nbsp;&nbsp;&nbsp;32 || 60&nbsp;&nbsp;&nbsp;96 || align=right | 2
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| [[#External interruption|External]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=81–82}} || 18&nbsp;&nbsp;&nbsp;24 || 58&nbsp;&nbsp;&nbsp;88 || align=right | 3
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| [[#Machine Check interruption|Machine Check]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=82–83}} || 30&nbsp;&nbsp;&nbsp;48 || 70&nbsp;&nbsp;112 || align=right | 1
|}
 
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===Input/Output interruption===
An I/O interruption<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=78–79}} occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for [[asynchrony (computing)|asynchronous]] events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the [[#Channel Status Word|CSW]] at ___location 64 ('40'X).
 
===Program interruption===
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| align=right | 1
| align=right | 1
| [[#Operation exception|Operation]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
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| align=right | 2
| align=right | 2
| [[#Privileged operation exception|Privileged operation]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
|-
| align=right | 3
| align=right | 3
| [[#Execute exception|Execute]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
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| align=right | 4
| align=right | 4
| [[#Protection exception|Protection]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=79}}
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| align=right | 5
| align=right | 5
| [[#Addressing exception|Addressing]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=79–80}}
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| align=right | 6
| align=right | 6
| [[#Specification exception|Specification]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
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| align=right | 7
| align=right | 7
| [[#Data exception|Data]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | 8
| align=right | 8
| [[#Fixed-point overflow exception|Fixed-point overflow]]<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=80}}
|-
| align=right | 9
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| title = IBM System/360 Principles of Operation
| id = A22-6821-7
| ref = {{sfnref|PoOps}}
| date = September 1968
| version = Eighth Edition
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