Capability Hardware Enhanced RISC Instructions: Difference between revisions

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{{Short description|Computer architecture for security}}
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'''Capability Hardware Enhanced RISC Instructions''' ('''CHERI''') is a computer processor technology designed to improve security. CHERI aims to address the root cause of the problems that are caused by a lack of [[memory safety]] in common implementations of languages such as [[C (programming language)|C]]/[[C++]], which are responsible for around 70% of security vulnerabilities in modern systems.<ref>{{cite web |url=https://www.zdnet.com/article/chrome-70-of-all-security-bugs-are-memory-safety-issues/ |publisher=ZDNet |title=Chrome: 70% of all security bugs are memory safety issues |date=22 May 2020 |access-date=24 January 2025}}</ref><ref>{{cite web |url=https://www.zdnet.com/article/microsoft-70-percent-of-all-security-bugs-are-memory-safety-issues/ |title= Microsoft: 70 percent of all security bugs are memory safety issues |publisher=ZDNet |date=11 February 2019 |access-date=24 January 2025}}</ref>