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=={{Anchor|SIS}}Software instruction sets==
Opcodes can be found in so-called [[byte code]]s and other representations intended for a software interpreter rather than a hardware device. These software-based instruction sets often employ slightly higher-level data types and operations than most hardware counterparts but are nevertheless constructed along similar lines. Examples include the byte code found in [[Java class file|Java class files,]] which are then interpreted by the [[Java virtual machine|Java Virtual Machine]] (JVM), the byte code used in [[GNU Emacs]] for compiled [[Lisp (programming language)|Lisp]] code, NET [[Common Intermediate Language]] (CIL), and many others.<ref name="bytecode"/>
==Sample opcode table==
This table shows opcodes of a simple 8-bit microprocessor, the [[Intel 8008]] from 1972.
Each opcode is 8 [[bit]]s long. Each is shown as a [[Binary number|binary]] pattern of ones and zeros in the '''Opcode''' column. Up to two additional fields may be embedded into the opcode. Some 3-bit fields are labeled DDD, SSS, CC, and ALU. The '''X''' in some fields means that either a 1 or 0 can be inserted with [[Don't-care term|no effect]].
The SSS (source) and DDD (destination) fields specify one of the eight possible 8008 [[Processor register|registers]] or memory: A, B, C, D, E, H, L, or M. CC specifies a condition that will activate certain JMP, CAL, and RET instructions. ALU specifies one of a possible eight [[arithmetic logic unit]] functions to be performed during an instruction, specifically, add, add with carry, subtract, subtract with borrow, logical AND, logical XOR, logical OR, and compare.
The fixed ones and zeros are combined with the parameter fields to build the 8-bit opcode. Additionally, the full instruction might require one or two additional bytes of operands. These are shown in the second major column of the table labeled '''Operands'''. If no operands are required, the column is filled with a dash (—).
Since the ones and zeros are difficult to remember, the '''Mnemonic''' column shows a short, easy to remember letter code that an [[assembly language]] programmer may use to invoke the required opcode.
The '''Description''' column shows the actual function performed by the microprocessor when it encounters this specific opcode.
{|class="wikitable" style="text-align:center"
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || — || — ||align=left| HLT ||align=left| Halt
|-
| 0 || 0 ||colspan=3|DDD || 0 || 0 || 0 || — || — ||align=left| INr ||align=left| DDD ← DDD + 1 (except A and M)
|-
| 0 || 0 ||colspan=3|DDD || 0 || 0 || 1 || — || — ||align=left| DCr ||align=left| DDD ← DDD - 1 (except A and M)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || — || — ||align=left| RLC ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || — || — ||align=left| Rcc (RET conditional) ||align=left| If cc true, P ← (stack)
|-
| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || ''data'' || — ||align=left| ADI ACI SUI SBI NDI XRI ORI CPI ''data'' ||align=left| A ← A [ALU operation] data
|-
| 0 || 0 ||colspan=3|N || 1 || 0 || 1 || — || — ||align=left| RST ''n'' ||align=left| (stack) ← P, P ← N x 8
|-
| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || — ||align=left| LrI ''data'' (Load r with immediate data) ||align=left| DDD ← data
|-
| 0 || 0 || X || X || X || 1 || 1 || 1 || — || — ||align=left| RET ||align=left| P ← (stack)
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| RRC ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
| 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || — || — ||align=left| RAL ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
| 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || — || — ||align=left| RAR ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| Jcc ''add'' (JMP conditional)||align=left| If cc true, P ← add
|-
| 0 || 1 || 0 || 0 ||colspan=3|port || 1 || — || — ||align=left| INP ''port'' ||align=left| A ← Port (ports 0-7 only)
|-
| 0 || 1 ||colspan=5|port || 1 || — || — ||align=left| OUT ''port'' ||align=left| Port ← A (ports 8-31 only)
|-
| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| Ccc ''add'' (CAL conditional)|| 9/11align=left| If cc true, (stack) ← P, P ← add
|-
| 0 || 1 || X || X || X || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| JMP ''add'' ||align=left| P ← add
|-
| 0 || 1 || X || X || X || 1 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| CAL ''add'' ||align=left| (stack) ← P, P ← add
|-
| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || — || — ||align=left| ADr ACr SUr SBr NDr XRr ORr CPr || align=left| A ← A [ALU operation] SSS
|-
| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || — || — ||align=left| Lds (Load d with s) ||align=left| DDD ← SSS
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || — || — ||align=left| HLT ||align=left| Halt
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Description
|-
!colspan=13|
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|-
|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left|ADr ADI (A ← A + arg)
|-
|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left|ACr ACI (A ← A + arg + Cy)
|-
|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left|SUr SUI (A ← A - arg)
|-
|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left|SBr SBI (A ← A - arg - Cy)
|-
|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left|NDr NDI (A ← A ∧ arg)
|-
|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left|XRr XRI (A ← A ⊻ arg)
|-
|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left|ORr ORI (A ← A ∨ arg)
|-
|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left|CPr CPI (A - arg)
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|}
==See also==
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