Synchronous dynamic random-access memory: Difference between revisions

Revision as of 20:49, 5 February 2025

Revision as of 16:19, 3 April 2025

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* Additional extended mode registers (selected by the bank address bits)

* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"

* DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer

* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command. A new signal {{overline|ACT}} controls it, during which the other control lines are used as row address bits 16, 15 and 14. When {{overline|ACT}} is high, other commands are the same as above.

== Construction and operation==

[[File:SDRAM_memory_module,_zoomed.jpg|thumb|SDRAM [[memory module]], zoomed]]

As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM ''chip'' internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.{{binpre}}

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}}

|-

! scope="row" | [[DDR SDRAM|DDR1]]

| {{Unbulleted list

| Access is ≥2 words

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}}

|-

! scope="row" | [[DDR2 SDRAM|DDR2]]

| Access is ≥4 words<br/> "Burst terminate" removed<br/> 4 units used in parallel<br/> {{Nowrap|1.25 - 5 ns}} per cycle<br/> Internal operations are at 1/2 the clock rate.<br/> Signal: [[Stub Series Terminated Logic|SSTL_18]] (1.8V)<ref name="edn-dramconsumer"/>

|-

! scope="row" | [[DDR3 SDRAM|DDR3]]

| Access is ≥8 words<br/> Signal: [[Stub Series Terminated Logic|SSTL_15]] (1.5V)<ref name="edn-dramconsumer"/><br/> Much longer CAS latencies

|-

! scope="row" | [[DDR4 SDRAM|DDR4]]

| {{Nowrap|V{{Sub|cc}} ≤ 1.2 V}} point-to-point (single module per channel)

|}

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'''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s. PC100 is [[backward compatible]] with PC66 and was superseded by the PC133 standard.

A module built out of 100&nbsp;MHz SDRAM chips is not necessarily capable of operating at 100&nbsp;MHz. The PC100 standard specifies the capabilities of the [[memory module]] as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.

==== PC133 ====