Atmel AVR instruction set: Difference between revisions

Revision as of 12:26, 10 February 2025

Revision as of 13:19, 11 February 2025

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== Instruction encoding ==

Bit assignments:

* {{not a typo|rrrrr / ddddd}} = Source/destination register

* {{not a typo|rrrr / dddd}} = Source/destination register (R16–R31)

* {{not a typo|rrr / ddd}} = Source/destination register (R16–R23)

* RRRR / DDDD = Source/destination register pair (R1:R0–R31:R30)

* {{not a typo|ddddd}} = Destination register

* {{not a typo|dddd}} = Destination register (R16–R31)

* {{not a typo|ddd}} = Destination register (R16–R23)

* DDDD = Destination register pair (R1:R0–R31:R30)

* pp = Register pair, W, X, Y or Z

* y = Y/Z register pair bit (0=Z, 1=Y)

* u = FMUL(SFMULS(U)) signedunsigned withbit (0=FMULS signed or, 1=FMULSU unsigned)

* s = Store/load bit (0=loadLD Rd,mem, 1=storeST mem,Rd)

* c = Call/jump (0=jump, 1=call)

* cy = With carry (0=without carry, 1=with carry)

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* {{not a typo|KKKKKKKK}} = 8-bit constant

The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/storemost withcommonly offsetencountered instructions areis the 5-bit source register field in bits 9 and 3–0. The most extreme example whereis the load/store with offset instructions, which break a 6-bit offset is broken into three pieces.

{|class="wikitable" style="text-align:center"

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! 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d ||colspan=4| opcode ||align=left| Load/store operations

|-

| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left rowspan=2| LDS rdRd,i/STS i,rdRd

|-

| colspan=16| 16-Bit immediate SRAM address i

|-bgcolor=lightgray

| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1s || 0 |colspan=5| 1d ||d xd ||d xd || 1 || 0 || 0 || 0 || (reserved)

|-

| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 0 || 1 ||align=left| LD/ST Rd through Z+/Y+

|-

| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 0 ||align=left| LD/ST Rd through −Z/−Y

|-bgcolor=lightgray

| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 1 || (reserved)

|-

| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 0 ||align=left| LPM/ELPM Rd,Z

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| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| RETI

|-bgcolor=lightgray

| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=2| 0 ||≠ 100 || x || 1 || 0 || 0 || 0 || (reserved)

|-bgcolor=lightgray

| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || x || x || 1 || 0 || 0 || 0 || (reserved)

|-

| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| SLEEP

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| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c || 0 || 0 || 0 || e || 1 || 0 || 0 || 1 ||align=left| Indirect jump/call to Z or EIND:Z

|-bgcolor=lightgray

| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c ||colspan=3| ≠ 000 || e || 1 || 0 || 0 || 1 || (reserved)

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| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 1 || 0 || 1 || 0 ||align=left| DEC Rd