Revision as of 23:07, 8 March 2025 edit Stephan Leeds (talk \| contribs) Extended confirmed users, IP block exemptions 35,964 edits →Examples: nonsense “Micro” to prefix “Micro-” where the latter is accurate ← Previous edit		Revision as of 23:07, 8 March 2025 edit undo Stephan Leeds (talk \| contribs) Extended confirmed users, IP block exemptions 35,964 edits →Examples: nonsense restrictive clause to accurate non-restrictive; random capitalization Next edit →
Line 52: * [[Processor register]]s{{dash}}the fastest possible access (usually 1 CPU cycle). A few thousand bytes in size * [[CPU cache\|Cache]] Level 0 (L0), [[~~Micro~~micro-operation]]s cache{{dash}}6,144 bytes (6 KiB{{cn\|reason=No source provided for IEC units, sources only use metric units like KB, MB, GB, etc\|date=May 2021}}{{Original research inline\|certain=y\|date=May 2021}})<ref>{{cite web\|url=http://www.anandtech.com/show/6355/intels-haswell-architecture/6 \|title=Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel \|publisher=AnandTech \|access-date=2014-07-31}}</ref> in size Level 1 (L1) [[Opcode\|Instruction]] cache{{dash}}128 KiB{{cn\|reason=No source provided for IEC units, sources only use metric units like KB, MB, GB, etc\|date=May 2021}}{{Original research inline\|certain=y\|date=May 2021}} in size ** Level 1 (L1) Data cache{{dash}}128 KiB{{cn\|reason=No source provided for IEC units, sources only use metric units like KB, MB, GB, etc\|date=May 2021}}{{Original research inline\|certain=y\|date=May 2021}} in size. Best access speed is around 700 [[Gigabyte\|GB]]/s<ref name=sisd_qa_f_mem_hsw>{{cite web\|url=http://www.sisoftware.co.uk/?d=qa&f=mem_hsw \|title=SiSoftware Zone \|publisher=Sisoftware.co.uk \|access-date=2014-07-31\|archive-url=https://web.archive.org/web/20140913231938/http://www.sisoftware.co.uk/?d=qa&f=mem_hsw\|archive-date=2014-09-13}}</ref>

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