Revision as of 23:25, 27 March 2025 edit Kvng (talk \| contribs) Extended confirmed users, New page reviewers 116,060 edits simplify link ← Previous edit		Revision as of 10:05, 10 April 2025 edit undo Ilo66 (talk \| contribs) 2 edits m Added a line to table to list a notable early industry DLP chip in 2016 with a reference to ISSCC 2017 paper Tag: Visual edit Next edit →
Line 129: \|1,056 Gops (16-bit) \|- \| rowspan="45" \|2016 \|DnnWeaver \|Georgia Tech Line 161: \| - \| - \|- \|Orlando<ref>{{Cite journal \|last=Desoli \|first=Giuseppe \|last2=Chawla \|first2=Nitin \|last3=Boesch \|first3=Thomas \|last4=Singh \|first4=Surinder-pal \|last5=Guidetti \|first5=Elio \|last6=De Ambroggi \|first6=Fabio \|last7=Majo \|first7=Tommaso \|last8=Zambotti \|first8=Paolo \|last9=Ayodhyawasi \|first9=Manuj \|last10=Singh \|first10=Harvinder \|last11=Aggarwal \|first11=Nalin \|date=2017-02 \|title=14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems \|url=https://ieeexplore.ieee.org/document/7870349/ \|publisher=IEEE \|pages=238–239 \|doi=10.1109/ISSCC.2017.7870349 \|isbn=978-1-5090-3758-2}}</ref> \|STMicroelectronics \|digital \|Convolution accelerator + DSP \|scratchpad \|RISC \| 676 Gops (16 bits) \|- \| rowspan="4" \|2017

Neural processing unit: Difference between revisions