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However, this distinction{{mdashb}}that power is provided by the bus{{mdashb}}is not the case in many [[avionics|avionic systems]], where data connections such as [[ARINC 429]], [[ARINC 629]], [[MIL-STD-1553B]] (STANAG 3838), and EFABus ([[STANAG 3910]]) are commonly referred to as ''data buses'' or, sometimes, ''databuses''. Such [[avionics#Aircraft networks|avionic data buses]] are usually characterized by having several [[Line-replaceable unit|Line Replaceable Items/Units]] (LRI/LRUs) connected to a common, shared [[Media (communication)|media]]. They may, as with ARINC 429, be [[Simplex communication|simplex]], i.e. have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be [[Duplex (telecommunications)|duplex]], allow all the connected LRI/LRUs to act, at different times ([[half duplex]]), as transmitters and receivers of data.<ref name="ASSC 2003">Avionic Systems Standardisation Committee, ''Guide to Digital Interface Standards For Military Avionic Applications'', ASSC/110/6/2, Issue 2, September 2003</ref>
The frequency or the speed of a bus is measured in Hz such as MHz and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there is a single transfer per clock cycle it is known as [[Single Data Rate]] (SDR), and if there are two transfers per clock cycle it is known as [[Double Data Rate]] (DDR) although the use of signalling other than SDR is uncommon outside of RAM. An example of this is PCIe which uses SDR.<ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> Within each data transfer there can be multiple bits of data. This is described as the width of a bus which is the number of bits the bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time.<ref>{{cite book | url=https://books.google.com/books?id=hDwDEAAAQBAJ&dq=bus+width&pg=PA54 | isbn=978-1-000-11716-5 | title=Foundations of Computer Technology | date=25 October 2020 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=j0wsBgAAQBAJ&dq=computer+bus+frequency&pg=PA39 | title=PC Systems, Installation and Maintenance | isbn=978-1-136-37442-5 | last1=Beales | first1=R. P. | date=11 August 2006 | publisher=Routledge }}</ref><ref>{{cite web | url=https://computer.howstuffworks.com/motherboard4.htm#:~:text=Bus%20speed%20usually%20refers%20to,dramatically%20affect%20a%20computer%27s%20performance | title=How Motherboards Work | date=20 July 2005 }}</ref> The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle.<ref>{{cite book | url=https://books.google.com/books?id=6FnMBQAAQBAJ&q=Data+rate&pg=PA92 | title=Computer Busses | isbn=978-1-4200-4168-2 | last1=Buchanan | first1=Bill | date=25 April 2000 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=vpnJDwAAQBAJ&q=Width | title=The Computer Engineering Handbook | isbn=978-1-4398-3316-2 | last1=Oklobdzija | first1=Vojin G. | date=5 July 2019 | publisher=CRC Press }}</ref> Alternatively a bus such as [[PCIe]] can use modulation or encoding such as [[PAM4]]<ref>{{Cite web |last=Robinson |first=Dan |date=2022-01-12 |title=Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023 |url=https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/
=== Bus multiplexing ===
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