C-element: Difference between revisions

Revision as of 22:19, 19 June 2025

Revision as of 22:33, 16 July 2025

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==Implementations of the C-element==

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit. Also, one should distinguish between single-output and dual-rail<ref>A. Mokhov, V. Khomenko, D. Sokolov and A. Yakovlev, [http://async.org.uk/tech-reports/NCL-EECE-MSD-TR-2010-162.pdf "On dual-rail control logic for enhanced circuit robustness"], IEEE Int. Conference on Application of Concurrency to System Design (ACSD) 2012, pp. 112–121.</ref> realizations of C-element. A dual-rail C-element can be realized on 2-input NANDs (NORs) only.<ref name="Varsh85">[https://www.researchgate.net/profile/Vuacheslav-Marakhovsky/publication/265767101_Functional_completeness_in_the_class_of_semimodular_circuits/links/54dfbec00cf2953c22b42dd7/Functional-completeness-in-the-class-of-semimodular-circuits.pdf V. Varshavskiy, M. Kishinevskiy, V. Marakhovskiy, L. Rozenblyum, "Functional completeness in the class of semimodular circuits," Soviet Journal of Computer and Systems Sciences, vol. 23, no. 6, pp. 70-80, 1985.]</ref> A single-output realization is workable if and only if:<ref>B. S. Tsirlin, "A Survey of Equivalent Problems of Realizing Circuits in the AND-NOT Basis that are Speed-Independent", Soviet Journal of Computer and Systems Sciences, vol. 24, 1986, pp. 58–69 (Б. С. Цирлин, [http://www.ee.bgu.ac.il/~kushnero/asynchronous/Varshavsky%20and%20Co/Tsirlin/Tsirlin_Review%20of%20realization%20problems%20in%20NAND%20basis.pdf "Обзор эквивалентных проблем реализации схем в базисе И-НЕ, не зависящих от скорости"] {{Webarchive|url=https://web.archive.org/web/20170729013055/http://www.ee.bgu.ac.il/~kushnero/asynchronous/Varshavsky%20and%20Co/Tsirlin/Tsirlin_Review%20of%20realization%20problems%20in%20NAND%20basis.pdf |date=2017-07-29 }}, Изв. АН СССР, Техническая кибернетика, №2, 1986, с. 159–171).</ref>

# The circuit, where each input of a C-element is connected through a separate inverter to its output, is semimodular relatively to the state, where all the inverters are excited.

# This state is live for the output gate of C-element.

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[[Image:Single_gate_C_elements.png|thumb|upright=2.2|Static implementations of two- and three-input C-element,<ref>I. E. Sutherland, [http://f-cpu.seul.org/new/micropipelines.pdf "Micropipelines]", Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989.</ref><ref>C. H. van Berkel, [http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=380B231B55BB4F45F6E4B72D4D273D44?doi=10.1.1.72.3108&rep=rep1&type=pdf "Beware the isochronic fork"], Report UR 003/91, Philips Research Laboratories, 1991.</ref><ref name="Mar10">V. B. Marakhovsky, [http://elib.spbstu.ru/dl/1945.pdf/download/1945.pdf Logic design of asynchronous circuits]. Slides on the course. CS&SE Department, SPbPU.</ref>]]

[[Image:Semistatic_C-elements.png|thumb|upright=1.7|Semistatic implementations of two- and multiple-input C-element.<ref>[http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=SU&NR=1562964A1&KC=A1&FT=D V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky, B. S. Tsirlin, "H flip-flop", USSR author's certificate SU1562964, Jul. 5, 1990.]</ref><ref>{{cite book | chapter-url=https://ieeexplore.ieee.org/document/665199 | doi=10.1109/GLSV.1998.665199 | chapter=β-driven threshold elements | title=Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222) | date=1998 | last1=Varshavsky | first1=V.I. | pages=52–58 | isbn=0-8186-8409-7 }}</ref><ref>[http://www.freepatentsonline.com/6338157.pdf V. I. Varshavsky, "Threshold element and method of designing the same," Patent US6338157, Jan. 8, 2002.]</ref> For a faster version see<ref>[https://worldwide.espacenet.com/publicationDetails/originalDocument?CC=RU&NR=2371842C2&KC=C2&FT=D& Y. A. Stepchenkov, Y. G. Dyachenko, A. N. Denisov, Y. P. Fomin, "H flip-flop", Patent RU2371842, Oct. 27, 2009.]</ref>]]

In his report<ref name="Mull55" /> Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible.<ref>D. Hampel, K. Prost, and N. Scheingberg, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=US&NR=3900742A&KC=A&FT=D&ND=3&date=19750819&DB=EPODOC&locale=en_EP "Threshold logic using complementary MOS device"], Patent US3900742, Aug. 19, 1975.</ref><ref>D. Doman, [http://samples.sainsburysebooks.co.uk/9781118273111_sample_406813.pdf Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon] {{Webarchive|url=https://web.archive.org/web/20151008213805/http://samples.sainsburysebooks.co.uk/9781118273111_sample_406813.pdf |date=2015-10-08 }}. Wiley, 2012, 327 p.</ref> Generally, C-elements with different timing assumptions<ref>K. S. Stevens, R. Ginosar and S. Rotem, [http://webee.technion.ac.il/~ran/papers/TVLSI-RelativeTiming-2002.pdf "Relative timing [asynchronous design<nowiki>]</nowiki>"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 1, pp. 129–140, 2003.</ref> can be built on [[AND-OR-Invert]] (AOI)<ref name="Zema62">H. Zemanek, [http://www.degruyter.com/view/j/itit.1962.4.issue-1-6/itit.1962.4.16.248/itit.1962.4.16.248.xml "Sequentielle asynchrone Logik"], Elektronische Rechenanlagen, vol. 4, no. 6, pp. 248–253, 1962. Also available in Russian as Г. Цеманек, [http://www.ee.bgu.ac.il/~kushnero/asynchronous/Zemanek.pdf "Последовательная асинхронная логика"] {{Webarchive|url=https://web.archive.org/web/20151005144323/http://www.ee.bgu.ac.il/~kushnero/asynchronous/Zemanek.pdf |date=2015-10-05 }}, Mеждународный симпозиум ИФАК Теория конечных и вероятностных автоматов 1962, с. 232—245.</ref><ref>W. Fleischhammer, [http://worldwide.espacenet.com/publicationDetails/originalDocument?CC=GB&NR=1199698A&KC=A&FT=D&ND=8&date=19700722&DB=EPODOC&locale=en_EP "Improvements in or relating to asynchronous bistable trigger circuits"], UK patent specification GB1199698, Jul. 22, 1970.</ref> or its dual, OR-AND-Invert (OAI) gate<ref>T.-Y. Wuu and S. B. K. Vrudhula, [https://ieeexplore.ieee.org/document/238414/ "A design of a fast and area efficient multi-input Muller C-element"], IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 215–219, 1993.</ref><ref>H. K. O. Berge, A. Hasanbegovic, S. Aunet, [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5783079 "Muller C-elements based on minority-3 functions for ultra low voltage supplies"], IEEE Int. Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2011, pp. 195–200.</ref> and inverter. Yet another option patented by Varshavsky et al.<ref>V. I. Varshavsky, A. Y. Kondratyev, N. M. Kravchenko, and B. S. Tsirlin, [https://worldwide.espacenet.com/publicationDetails/originalDocument?CC=SU&NR=1411934A1&KC=A1&FT=D&ND=3&date=19880723&DB=EPODOC&locale=en_EP "H flip-flop"], USSR Author's certificate SU1411934 Jul. 23, 1988.</ref>

<ref>V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky and B. S. Tsirlin, [https://worldwide.espacenet.com/publicationDetails/originalDocument?CC=SU&NR=1443137A1&KC=A1&FT=D&ND=3&date=19881207&DB=EPODOC&locale=en_EP "H flip-flop"], USSR Author's certificate SU1443137, Dec. 7, 1988.</ref> is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Connecting an additional majority gate to the inverted output of C-element, we obtain ''inclusive'' OR (EDLINCOR) function:<ref>{{cite journal | url=https://doi.org/10.1049/ip-e.1993.0018 | doi=10.1049/ip-e.1993.0018 | title=Event-driven logic (EDL) approach to digital systems representation and related design processes | date=1993 | last1=Pucknell | first1=D.A. | journal=IEE Proceedings E - Computers and Digital Techniques | volume=140 | issue=2 | pages=119–126 | url-access=subscription }}</ref><ref>A. Yakovlev, M. Kishinevsky, A. Kondratyev, L. Lavagno, M. Pietkiewicz-Koutny, [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.19.4630&rep=rep1&type=pdf "On the models for asynchronous circuit behaviour with OR causality"], Formal Methods in System Design, vol. 9, no. 3, pp. 189—233. 1996.</ref> <math>z_n = x_1 x_2 + (x_1 + x_2) \overline{y_n}</math>. Some simple asynchronous circuits like pulse distributors<ref>J. C. Nelson, [https://archive.org/stream/speedindependent71nels#page/n5/mode/2up Speed-independent counting circuits]. Report no. 71, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.</ref> can be built solely on majority gates.