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TLM-2.0 was subsequently incorporated into the [[IEEE]] 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.<ref name="IEEE_1666_2011">{{cite standard |title=IEEE Standard for Standard SystemC Language Reference Manual |standard=IEEE Std 1666-2011 |publisher=IEEE |year=2012 |doi=10.1109/IEEESTD.2012.6134619}}</ref>
===Industry Adoption and Commercial Tools===
By the mid-2000s, major [[Electronic Design Automation|EDA]] companies began incorporating TLM support into their commercial tools. [[Mentor Graphics]] (now [[Siemens EDA]]) introduced TLM support in their ModelSim simulator in 2004,<ref name="ModelSim_TLM">{{cite news |title=Mentor Graphics Adds SystemC TLM to ModelSim |newspaper=EE Times |date=2004-03-15}}</ref> followed by [[Cadence Design Systems]] with their Incisive platform in 2005.<ref name="Cadence_TLM">{{cite press release |title=Cadence Introduces Transaction-Level Modeling Flow |publisher=Cadence Design Systems |date=2005-09-12}}</ref>
Virtual platform companies such as [[CoWare]] (acquired by Synopsys in 2010),<ref name="Synopsys_CoWare">{{cite news |title=Synopsys Acquires CoWare for Virtual Prototyping |newspaper=EE Times |date=2010-02-22}}</ref> Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.<ref name="Virtual_Platform_Market">{{cite report |title=Virtual Prototyping Market Analysis |publisher=Gary Smith EDA |year=2010}}</ref>
===Modern Developments (2010s-Present)===
The 2010s saw TLM become standard practice in the semiconductor industry, particularly for [[ARM architecture|ARM]]-based SoC design. [[ARM Holdings]] released comprehensive TLM models of their processor architectures, including [[ARM Cortex-A]] and [[ARM Cortex-M]] series processors.<ref name="ARM_TLM_Models">{{cite white paper |title=ARM Fast Models: System-Level Modeling for Software Development |publisher=ARM Holdings |year=2012}}</ref>
The rise of [[artificial intelligence]] and [[machine learning]] accelerators in the late 2010s created new demands for TLM modeling, leading to specialized libraries and methodologies for modeling [[neural processing unit]]s and other AI hardware.<ref name="AI_TLM">{{cite conference |title=Transaction-Level Modeling for AI Accelerator Design |author=Chen, Li |conference=Design Automation Conference |year=2019 |pages=1-6 |doi=10.1145/3316781.3317788}}</ref>
In 2020, OSCI merged with [[Accellera]], consolidating SystemC and TLM development under a single organization and ensuring continued evolution of the standards.<ref name="Accellera_OSCI_Merger">{{cite press release |title=Accellera and OSCI Merge to Advance System-Level Design Standards |publisher=Accellera Systems Initiative |date=2020-01-15}}</ref>
==Key Concepts==
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