Transaction-level modeling: Difference between revisions

Revision as of 01:26, 20 June 2025

Revision as of 14:25, 20 June 2025

Line 10:

==Background and History==

===Early Development (1990s-2000s)===

Transaction Level Modeling emerged in the late 1990s and early 2000s as a direct response to the increasing complexity of [[System-on-a-chip|system-on-chip]] designs and the limitations of traditional [[Register-transfer level|register-transfer level]] (RTL) modeling for system-level verification and software development.<ref name="Gajski_ESL">{{cite book |title=SpecC: Specification Language and Methodology |author=Gajski, Daniel D. |publisher=Kluwer Academic Publishers |year=2000 |isbn=978-0-7923-7822-5}}</ref> The semiconductor industry was experiencing a a widening disparity between design complexity and designer productivity.<ref name="ITRS_Design">{{cite report |title=International Technology Roadmap for Semiconductors: Design |publisher=Semiconductor Industry Association |year=1999 |url=http://www.itrs.net/}}</ref>

The foundational concepts of TLM were developed simultaneously by several research groups and companies. [[Cadence Design Systems]] introduced early transaction-level concepts in their [[SpecC]] language in the mid-1990s,<ref name="SpecC_Origins">{{cite conference |title=SpecC: A Design Language for System Level Design |author=Gajski, Daniel D. |conference=Design Automation Conference |year=1997 |pages=464-469 |doi=10.1145/266021.266138}}</ref> while [[Synopsys]] developed similar concepts in their [[SystemC]] methodology starting in 1999.<ref name="SystemC_History">{{cite journal |title=SystemC: Past, Present, and Future |author=Grötker, Thorsten |journal=IEEE Design & Test |volume=20 |issue=6 |pages=72-77 |year=2003 |doi=10.1109/MDT.2003.1246169}}</ref>