* Practical existing implementations of BCD are typically slower than operations on binary representations, especially on embedded systems, due to limited processor support for native BCD operations.<ref name="Mathur_1989" />
* Some operations are more complex to implement. [[Adder (electronics)|Adder]]s require extra logic to cause them to wrap and generate a carry early. Also, 15 to 20 per cent% more circuitry is needed for BCD add compared to pure binary.{{Citation needed|date=May 2011}} Multiplication requires the use of algorithms that are somewhat more complex than shift-mask-add (a [[Binary numeral system#Multiplication|binary multiplication]], requiring binary shifts and adds or the equivalent, per-digit or group of digits is required).
* Standard BCD requires four bits per digit, roughly 20 per cent% more space than a binary encoding (the ratio of 4 bits to log<sub>2</sub>10 bits is 1.204). When packed so that three digits are encoded in ten bits, the storage overhead is greatly reduced, at the expense of an encoding that is unaligned with the 8-bit byte boundaries common on existing hardware, resulting in slower implementations on these systems.<!-- Could add: encoding or decoding is trivial in software using a table lookup, and fast using direct logic otherwise. In hardware, it requires no more than three gate delays. -->
