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[[File:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|right|CMOS 1-[[megabit]] (Mbit) DRAM chip, one of the last models developed by [[VEB Carl Zeiss Jena]], in 1989]]
In 1966, [[Robert Dennard]], while examining the characteristics of MOS technology, found it was capable of building [[capacitor]]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, and the MOS transistor could control writing the charge to the capacitor. This led to his development of modern DRAM architecture for which there is a single MOS transistor per capacitor.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="ibm100" /><ref name="Robert Dennard"/> The first commercial DRAM IC chip was the [[Intel 1103]], which was [[Semiconductor manufacturing process|manufactured]] on an [[10 μm process|8{{nbsp}}μm]] MOS process with a capacity of 1{{nbsp}}[[Kilobit|kbit]], and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=Who Invented the Intel 1103 DRAM Chip? |access-date=2025-03-03 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead }}</ref>
The earliest DRAMs were often synchronized with the CPU clock and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book |author=P. Darche |url=https://books.google.com/books?id=rLC9zQEACAAJ |title=Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer |year=2020 |isbn=9781786305633 |page=59| publisher=John Wiley & Sons }}</ref><ref>{{cite book |author1=B. Jacob |url=https://books.google.com/books?id=SrP3aWed-esC |title=Memory Systems: Cache, DRAM, Disk |author2=S. W. Ng |author3=D. T. Wang |publisher=Morgan Kaufmann |year=2008 |isbn=9780080553849 |page=324}}</ref> In 1992 Samsung released KM48SL2000, which had a capacity of 16{{nbsp}}[[Mbit]].<ref name="electronic-design">{{cite journal |title=Electronic Design |journal=[[Electronic Design]] |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref><ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref> The first commercial [[double data rate]] SDRAM was Samsung's 64{{nbsp}}Mbit [[DDR SDRAM]], released in June 1998.<ref>{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref> [[GDDR]] (graphics DDR) is a form of [[SGRAM]] (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mbit memory chip in 1998.<ref>{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref>
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|10 mm<sup>2</sup>
|<ref name="Intel2003">{{cite web |title=Intel: 35 Years of Innovation (1968–2003) |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf |publisher=Intel |year=2003 |access-date=26 June 2019}}</ref><ref name="HC">[http://history-computer.com/ModernComputer/Basis/dram.html ''The DRAM memory of Robert Dennard''] {{Webarchive|url=https://web.archive.org/web/20200801004808/https://history-computer.com/ModernComputer/Basis/dram.html |date=2020-08-01 }} history-computer.com</ref><ref name="Lojek-1103">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=362–363 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA362 |quote=The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm<sup>2</sup> memory cell size, a die size just under 10 mm<sup>2</sup>, and sold for around $21.}}</ref>
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| rowspan="2" |<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-date=2 November 2023|archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html|url-status=dead}}</ref>
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|1993
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