Single instruction, multiple threads: Difference between revisions

Content deleted Content added
WikiCleanerBot (talk | contribs)
m v2.05b - Bot T19 CW#83 - Fix errors for CW project (Heading start with three "=" and later with level two)
Citation bot (talk | contribs)
Alter: url, title. URLs might have been anonymized. | Use this bot. Report bugs. | Suggested by Abductive | Category:Articles needing cleanup from July 2025 | #UCB_Category 21/325
Line 17:
 
The key difference between SIMT and [[SIMD lanes]] is that each of the Processing Units in the SIMT Array have their own local memory, and may have a completely different Stack Pointer (and thus perform computations on completely different data sets), whereas the ALUs in SIMD lanes know nothing about memory per se, and have no [[register file]].
This is illustrated by the [[ILLIAC IV]]. Each SIMT core was termed a Processing Element, and each PE had its own separate Memory (PEM). Each PE had an "Index register" which was an address into its PEM.<ref>{{Cite web|url=https://www.researchgate.net/publication/2992993_The_Illiac_IV_system2992993|title=(PDF) The Illiac IV system}}</ref><ref name="auto"/>
In the [[ILLIAC IV]] the Burroughs B6500 primarily handled I/O, but also sent instructions to the Control Unit (CU) which would then handle the broadcasting to the PEs. Additionally the B6500, in its role as an I/O processor, had access to ''all'' PEMs.