Content deleted Content added
→{{Anchor|REGISTER-PRESSURE}}Register pressure: On CPUs with cache, register spillage often ends up in cache. |
Guy Harris (talk | contribs) →Control flow operations: A skip is more like a forward conditional branch with a fixed offset; for predication I tend to think of the predicate as being part of the instruction itself, rather than the previous instruction. They can skip more than one instruction (the IBM 704 and successors had a "Compare Accumulator and Storage" instruction that skipped either 0, 1, or 2 instructions based on whether AC < M, AC = M, or AC > M). |
||
Line 59:
*''[[Conditional branch|Conditionally branch]]'' to another ___location if a certain condition holds.
*''[[Indirect branch|Indirectly branch]]'' to another ___location.
*''Skip'' one
*''Trap'' Explicitly cause an [[interrupt]], either conditionally or unconditionally.
*''[[Subroutine|Call]]'' another block of code, while saving, e.g., the ___location of the next instruction, as a point to return to.
| |||