Flash memory: Difference between revisions

Revision as of 13:13, 17 August 2025

Latest revision as of 19:18, 25 August 2025

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{{Main|Charge trap flash}}

[[Charge trap flash]] (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.<ref name="electronicdesign-20130415">{{Cite news |last=Wong |first=Bill |date=15 April 2013 |title=Interview: Spansion's CTO Talks About Embedded Charge Trap NOR Flash Technology |work=Electronic Design |url=https://www.electronicdesign.com/technologies/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |url-status=live |archive-url=https://web.archive.org/web/20231204125719/https://www.electronicdesign.com/technologies/embedded/digital-ics/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |archive-date=4 December 2023 }}</ref><ref name="ito-taito-2017">{{Cite book |last1=Ito |first1=Takashi |title=Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations |last2=Taito |first2=Yasuhiko |date=9 September 2017 |publisher=[[Springer Publishing]] |isbn=978-3-319-55306-1 |editor-last=Hidaka |editor-first=Hideto |series=Integrated Circuits and Systems |pages=209–244 |chapter=SONOS Split-Gate eFlash Memory |doi=10.1007/978-3-319-55306-1_7 }}</ref><ref name="ieee-91-4">{{Cite journal |last1=Bez |first1=Roberto |last2=Camerlenghi |first2=E. |last3=Modelli |first3=Alberto |last4=Visconti |first4=Angelo |date=April 2003 |title=Introduction to flash memory |journal=[[Proceedings of the IEEE]] |publisher=[[Institute of Electrical and Electronics Engineers]] |volume=91 |issue=4 |pages=498–502 |doi=10.1109/JPROC.2003.811702 |bibcode=2003IEEEP..91..489B }}</ref><ref name="lee-2011">{{Cite journal |last=Lee |first=Jang-Sik |date=18 October 2011 |title=Review paper: Nano-floating gate memory devices |journal=Electronic Materials Letters |publisher=Korean Institute of Metals and Materials |volume=7 |issue=3 |pages=175–183 |doi=10.1007/s13391-011-0901-5 |bibcode=2011EML.....7..175L |s2cid=110503864 }}</ref><ref name="auto5">{{Cite web |last=Aravindan |first=Avinash |date=13 November 2018 |title=Flash 101: Types of NAND Flash |url=https://www.embedded.com/flash-101-types-of-nand-flash/ |url-status=live |archive-url=https://web.archive.org/web/20231106101540/https://www.embedded.com/flash-101-types-of-nand-flash/ |archive-date=6 November 2023 |website=embedded.com }}</ref><ref name="nanoscale-9-1-526">{{Cite journal |last1=Meena |first1=Jagan Singh |last2=Sze |first2=Simon Min |last3=Chand |first3=Umesh |last4=Tseng |first4=Tseung-Yuen |date=25 September 2014 |title=Overview of emerging nonvolatile memory technologies |journal=Nanoscale Research Letters |volume=9 |issue=1 |page=526 |doi=10.1186/1556-276x-9-526 |issn=1556-276X |id=526 |doi-access=free |pmid=25278820 |pmc=4182445 |bibcode=2014NRL.....9..526M }}</ref>

Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology, however, still uses a tunneling oxide and blocking layer, which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).<ref name="techtarget-20230619">{{Cite web |last=Sheldon |first=Robert |date=19 June 2023 |title=Charge trap technology advantages for 3D NAND flash drives |url=https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |url-status=live |archive-url=https://web.archive.org/web/20230809223937/https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |archive-date=9 August 2023 |website=SearchStorage }}</ref><ref name="grossi-zambelli-olivo-2016">{{Cite book |last1=Grossi |first1=A. |title=3D Flash Memories |last2=Zambelli |first2=C. |last3=Olivo |first3=P. |date=7 June 2016 |publisher=[[Springer Science+Business Media]] |isbn=978-94-017-7512-0 |editor-last=Micheloni |editor-first=Rino |___location=Dordrecht |pages=29–62 |chapter=Reliability of 3D NAND Flash Memories |doi=10.1007/978-94-017-7512-0_2 }}</ref>

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====Erasing====

To erase a NOR flash cell (resetting it to the "1" state), a large voltage ''of the opposite polarity'' is applied between the CG and source terminal, pulling the electrons off the FG through [[Fowler–Nordheim tunneling]] (FN tunneling).<ref>{{cite book | url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+erase&pg=PA55 | isbn=978-3-030-79827-7 | title=Springer Handbook of Semiconductor Devices | date=10 November 2022 | publisher=Springer }}</ref> This is known as Negative gate source source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing the cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source.<ref>{{cite book | url=https://books.google.com/books?id=2E0r6BRo2VkC&dq=nor+flash+erase&pg=PA212 | isbn=978-90-481-9216-8 | title=CMOS Processors and Memories | date=9 August 2010 | publisher=Springer }}</ref><ref>{{cite journal | url=https://ieeexplore.ieee.org/document/1035946 | title= High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories| date= 2002| doi=10.1109/JSSC.2002.803045 | last1= Tanzawa| first1= T.| last2= Takano| first2= Y.| last3= Watanabe| first3= K.| last4= Atsumi| first4= S.| journal= IEEE Journal of Solid-State Circuits| volume= 37| issue= 10| pages= 1318–1325| bibcode= 2002IJSSC..37.1318T| url-access= subscription}}</ref> Modern NOR&nbsp;flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together.<ref>{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+erase+block&pg=PA41 | isbn=978-94-007-6082-0 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | date=12 September 2013 | publisher=Springer }}</ref> Programming of NOR cells, however, generally can be performed one byte or word at a time.

{{clear}}

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An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.<ref name="vnand" />

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND&nbsp;flash memory is configured.<ref name="vnand" /> There is also string stacking, which builds several 3D NAND memory arrays or "plugs"<ref>{{Cite web|url=https://blocksandfiles.com/2023/08/18/samsung-has-300-layer-nand-coming-with-430-layers-after-that/|title=Samsung has 300-layer NAND coming, with 430 layers after that – report|first=Chris|last=Mellor|date=18 August 2023}}</ref> separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.<ref name="auto8"/><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/9282426|title=2020 China Semiconductor Technology International Conference (CSTIC)|doi=10.1109/CSTIC49141.2020.9282426 |chapter=Manufacturing Challenges and Cost Evaluation of New Generation 3D Memories |date=2020 |last1=Dube |first1=Belinda Langelihle |pages=1–3 |isbn=978-1-7281-6558-5 |s2cid=229376195 }}</ref><ref name="auto9">{{Cite web |last=Choe |first=Jeongdong |date=2019 |title=Comparison of Current 3D NAND Chip & Cell Architecture |url=https://files.futurememorystorage.com/proceedings/2019/08-07-Wednesday/20190807_FTEC-202-1_Choe.pdf |pages=21, 24}}</ref>

====Construction====

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====Cost====

[[File:3D NAND minimum cost example.png|thumb|right|300px|'''Minimum bit cost of 3D NAND from non-vertical sidewall.''' The top opening widens with more layers, counteracting the increase in bit density.]]

The wafer cost of a 3D NAND is comparable with scaled down (32&nbsp;nm or less) planar NAND flash.<ref>{{cite web|url=https://www.linkedin.com/pulse/toshibas-cost-model-3d-nand-frederick-chen|title=Toshiba's Cost Model for 3D NAND|website=www.linkedin.com}}</ref> However, with planar NAND scaling stopping at 16&nbsp;nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.<ref>{{cite web |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |url=https://www.linkedin.com/pulse/calculating-maximum-density-equivalent-2d-design-rule-frederick-chen |website=linkedin.com |access-date=1 June 2022}}; {{cite web |url=https://semiwiki.com/lithography/296121-calculating-the-maximum-density-and-equivalent-2d-design-rule-of-3d-nand-flash/ |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |website=semwiki.com |date=21 February 2021 |access-date=1 June 2022}}</ref>

==Limitations==

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[[File:Micron_45_nm_NOR_Flash_Data_Retention.png|thumb|right|300px|45nm NOR flash memory example of data retention varying with temperatures]]

Data stored on flash cells is steadily lost due to electron detrapping{{Definition needed|data detrapping is not a familiar concept to the average wikipedia reader.|date=December 2022}}. The rate of loss increases exponentially as the [[absolute temperature]] increases. For example: For a 45&nbsp;nm NOR flash, at 1000 hours, the threshold voltage (Vt) loss at 25°C is about half that at 90°C.<ref>{{cite book

| last1 = Calabrese |first1 =Marcello|title =Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)|chapter =Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology| date = May 2013 | chapter-url = https://ieeexplore.ieee.org/document/6563298 |pages =37–40| doi = 10.1109/ICICDT.2013.6563298 |isbn =978-1-4673-4743-3|s2cid =37127243| access-date = June 22, 2022}}</ref>

===Memory wear===