Random-access memory: Difference between revisions

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The '''memory wall''' is the growing disparity of speed between CPU and the response time of memory (known as [[memory latency]]) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 1986 to 2000, [[CPU]] speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming [[bottleneck (engineering)|bottleneck]] in computer performance.<ref>The term was coined in {{cite web |url=http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |title=Archived copy |access-date=2011-12-14 |url-status=live |archive-url=https://web.archive.org/web/20120406111104/http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |archive-date=2012-04-06}}.</ref>

Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today'sModern CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.

CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. [[Intel]] summarized these causes in a 2005 document.<ref>{{Cite web |title= Platform 2015: Intel Processor and Platform Evolution for the Next Decade |date= March 2, 2005 |url= http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |url-status= live |archive-url= https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |archive-date= April 27, 2011 }}</ref>

<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor [[leakage current]] increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called [[von Neumann bottleneck]]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, [[RC time constant#Delay|resistance-capacitance]] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>