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The dynamic logic circuit requires two phases. The first phase, when ''Clock'' is low, is called the ''setup phase'' or the ''precharge phase'' and the second phase, when ''Clock'' is high, is called the ''evaluation phase''. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs ''A'' and ''B''). The [[capacitor]], which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.
During the evaluation phase, ''Clock'' is high. If ''A'' and ''B'' are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).
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