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==Purpose==
Memory controllers contain the logic necessary to read and write [[dynamic RAM]], and to "refresh" the DRAM by sending current through the entire device. Without constant refreshes, DRAM will lose the data written to it as the [[capacitors]] leak their [[charge]] within a number of milliseconds (64 milliseconds according to [[JEDEC]] standards).
Reading and writing to DRAM is facilitated by use of [[multiplexer]]s and [[demultiplexer]]s, by selecting the correct row and column address as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM can select the correct memory ___location and return the data (once again passed through a multiplexer to reduce the number of wires necessary to assemble the system).
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