Tomasulo's algorithm: Difference between revisions

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Delete a copyvio example. I found this same example in one of my textbooks that is so old it is falling apart.
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*Instructions are issued sequentially so that the effects of a sequence of instructions,<s> such as exceptions raised,</s> occur in the same order as they would in a non-pipelined processor, regardless of the fact that they are being executed non-sequentially.
 
*All general-purpose and [[Reservation_stations|reservation station]] registers hold either real or virtual values. If a real value is unavailable to a destination register during the issue stage, a virtual value is initially used. The functional unit that is computing the real value is assigned as the virtual value. The virtual register values are converted to real values as soon as the designated functional unit completes its computation.
 
*Functional units use [[Reservation_stations|reservation stations]] with multiple slots. Each slot holds information needed to execute a single instruction, including the operation and the operands. The functional unit begins processing when it is free and when all source operands needed for an instruction are real.
 
==Instruction Lifecycle==