Address decoder: Difference between revisions

Revision as of 22:46, 18 April 2008

Revision as of 12:29, 5 May 2008

Line 2:

Address decoders are fundamental building blocks for systems that use buses. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.^^

{{compu-hardware-stub}}

[[Category:Digital electronics| ]]

[[de:Adressdekoder]]

[[pt:Decodificador de endereços]]

{{compu-hardware-stub}}