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Line 8: The following are the concepts necessary to the implementation of Tomasulo's Algorithm. Instructions are issued sequentially so that the effects of a sequence of instructions~~,<s>~~ such as exceptions raised~~,</s>~~ by these instructions occur in the same order as they would in a non-pipelined processor, regardless of the fact that they are being executed non-sequentially. All general-purpose and [[Reservation_stations\|reservation station]] registers hold either real or virtual values. If a real value is unavailable to a destination register during the issue stage, a virtual value is initially used. The functional unit that is computing the real value is assigned as the virtual value. The virtual register values are converted to real values as soon as the designated functional unit completes its computation.

Tomasulo's algorithm: Difference between revisions