Application-specific instruction set processor: Difference between revisions

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References: Added IEEE reference regarding Chess/Checkers (IP Designer) from Gert Goossens, et al.
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Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[FPGA]] or during the chip synthesis.
 
==References Literature ==
* {{cite book |title=Design of ASIPs in Multi-Processor SoCs using the Chess/Checkers Retargetable Tool Suite |author=Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet |year=2006 |publisher=IEEE | journal=Proceedings of the International Symposium on System-on-Chip | pages=61-64 |___location=Piscataway, NJ |isbn=1-4244-0621-8 }}
* {{cite book |title=Customizable Embedded Processors |author=Paolo Ienne, Rainer Leupers (eds.) |year=2006 |publisher=Morgan Kaufmann |___location=San Mateo, CA |isbn=978-0-12-369526-0 }}
* {{cite book |title=Building ASIPs: The Mescal Methodology |author=Matthias Gries, Kurt Keutzer (eds.) |year=2005 |publisher=Springer |___location=New York |isbn=978-0-387-26057-0 }}
* {{cite book |title=Optimized ASIP Synthesis from Architecture Description Language Models |author=Oliver Schliebusch, Heinrich Meyr, Rainer Leupers |year=2007 |publisher=Springer |___location=Dordrecht |isbn=978-1-4020-5685-7 }}
* {{cite journal | author=M. Jain, M. Balakrishnan, A. Kumar | title=ASIP Design Methodologies: Survey and Issues | publisher=IEEE | year=2001 | journal=Proceedings of the Fourteenth International Conference on VLSI Design | pages=76—81 }}
* {{cite bookjournal |title=Design of ASIPs in Multi-Processor SoCs using the Chess/Checkers Retargetable Tool Suite |author=Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet |year=2006 |publisher=IEEE | journal=Proceedings of the International Symposium on System-on-Chip | pages=61-6461–64 |___location=Piscataway, NJ |isbn=1-4244-0621-8 }}
 
{{CPU technologies}}