26-bit computing: Difference between revisions

Revision as of 08:35, 14 August 2008

Revision as of 17:21, 18 September 2008

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In [[ARM Limited|ARM]] [[ARM_architecture|processor architecture]], '''26-bit''' refers to the design used in the original ARM processors, where the [[Program Counter]]('''PC''') and [[Status_register|Processor Status Register]]('''PSR''') were combined into one 32-bit [[Processor_registers|register]] (R15), the Status flags filling the high 6 bits and the Program Counter taking up the lower "26" bits.

Infact, because the Program Counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The 4 modes allowed were USR26; SVC26; IRQ26; FIQ26, contrast this with the 32 possible modes available when the program status was seperatedseparated from the program counter in more recent [[ARM Architecture|ARM architectures]].

This design enabled more efficient [[Computer_program|program]] execution, as the Program Counter and Status flags could be saved and restored with a single operation. This resulted in faster [[subroutine]] calls and [[interrupt]] response than traditional designs, which would have to do two register load/saves when calling or returning from a subroutine.