Open Artwork System Interchange Standard: Difference between revisions

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A cell can be a simple (NAND, OR, XOR, etc.) logic circuit or it can comprise as much as the entire functionality for an embedded microprocessor. The content of the cell is arbitrarily defined according to its anticipated use when connected with other cells during logic design. Mostly, a Library OASIS<sup>®</sup> file contains layer-by-layer transistor-level geometric (polygons) and non-geometric data that represents how, at the cell level, the cell should be manufactured. Not all cells within a cell Library are used in a single design.
 
A finished logic design shows how a set of cells chosen from a cell Library for a particular design are to be connected. Chip-level layout design uses a Netlist from Logic design to place cell-level OASIS<sup>®</sup> Library files from the same library used in Logic design and then add the routing that connects the placed cells together as one integrated circuit. After chip-level optimizations are made, the final output is a single OASIS data file containing optimized but still raw placement, routing and cell layer data for the entire integrated circuit.
 
Typically, the raw design layout data represented as OASIS<sup>®</sup> still requires finishing so that the layout, when transformed from data to shaped flashing beams of light and electrons actually print onto a mask or wafer as intended. For designs that are more advanced, the edges and the corners of the circuit features require a correction because they are too close to each other to be resolved lithographically without a correction. Furthermore, at least some of the features will be so small that without a correction, they will not expose evenly. The corrections are addedcalled toOptical theProximity contentCorrection of(OPC) theand rawScatterbar OASIS(Assist datafeature) design representationcorrections. The corrections are calledadded Opticalto Proximitythe Correctioncontent (OPC)of andthe Scatterbarraw (AssistOASIS feature)data correctionsdesign representation.
 
Other adjustments to the data are made which are not covered here. However, once finished, the modified layout of the chip is fractured from a polygon-based representation to a geometrically equivalent representation of the data using smaller (machine-printable) geometric shapes. The fractured data is stored separately as a fractured OASIS data file. In some cases, the corrections plus fracturing can increase the size of the modified and fractured OASIS data file by as much as 10X.