Cell microprocessor implementations: Difference between revisions

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Sony, IBM and Toshiba [http://www.theregister.co.uk/2006/01/12/ibm_sony_toshiba_32nm_cell/ already announced] to begin work on a Cell as small as 32nm back in January 2006, but since process shrinks in fabs usually happen on a global and not an individual chip scale, this is to be seen merely as a public commitment to take Cell to 32nm.
 
IBM could elect to partially redesign the chip to take advantage of additional silicon area in future revisions to make the size small. The Cell architecture already makes explicit provisions for the size of the local store to vary across implementations. A chip-level interface is available to the programmer to determine local store capacity, which is always an exact binary power.
 
It would be feasible to double the local store to 512 KiB per SPU leaving the total die area devoted to the SPU processors roughly unchanged. In this scenario, the SPU area devoted to the local store would increase to 60% while other areas shrink by half. Going this route would reduce heat, and increase performance on memory intensive workloads, but without yielding IBM much if any reduction in cost of manufacture.