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Traditionally, dynamic random access memory ([[DRAM]]) has an asynchronous interface which means that data propagated through nested gates (transistors) to get the memory cell as quickly as the gates could propagate the data. SDRAM has a synchronous interface, meaning that these gates are synchronized with computer's system bus [[clock signal]], allowing timing optimization to reduce those propagation delays.
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[[User:Davea0511|Davea0511]] ([[User talk:Davea0511|talk]]) 18:04, 5 September 2009 (UTC)
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