Placement (electronic design automation): Difference between revisions

Revision as of 22:13, 19 December 2005

Revision as of 22:17, 19 December 2005

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a number of objectives to ensure that a circuit meets its performance demands. Typical placement

objectives include

*Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength and wirelength squaresquared, respectively.

*Timing: The [[Clock signal | clock]] cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay.

*Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours.

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*Another thread of placement techniques started with the proposal of [[simulated annealing]] as a general combinatorial optimization technique.

== References ==

*''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin, and Scheffer, ISBN 0849330963 Old fashioned (paper) survey of the field, from which the above summary was derived, with permission.