Hybrid-core computing: Difference between revisions

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{{Userspace draft|date=November 2009}}

'''Hybrid-core''' iscomputing is the technique of extending a commodity [[instruction set architecture (ISA)]] (e.g. [[x86]]) with application-specific instructions to accelerate application performance. It is a form of [[heterogeneous computing]] wherein multiple computational units (i.e. graphics processing unit (GPU)), or custom acceleration logic (application-specific integrated circuit ([[ASIC]]) or field-programmable gate array ([[FPGA]])) coexist with a "commodity" processor.

Hybrid-core processing differs from general heterogeneous computing<ref>Heterogeneous Processing: a Strategy for Augmenting Moore's Law". Linux Journal., RetrievedJanuary 2007-10-03.2006</ref> in that the computational units share a common logical address space, are cache coherent and an executable the is composed of a single instruction stream—in essence a contemporary [[coprocessor]]. The instruction set contains instructions that can be dispatched either to the host instruction set or to the application-specific hardware.<ref>"Convey Computer Corp. "The Convey HC-1 Computer Architecture Overview"</ref>

Typically, hybrid-core computing is used to accelerate applications beyond what is currently physically possible with off-the-shelf processors (i.e., to circumvent obstacles such as the memory-wall and power-wall), or to reduce power & cooling costs in a data center by reducing computational footprint.