Pulse transition detector: Difference between revisions

Revision as of 16:29, 3 January 2010

Revision as of 14:33, 14 June 2010

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The PTD consists of a delay gate (which delays the [[clock signal]]) and the clock signal itself passed through a [[NAND gate]] and then inverted.

The benefit of edge triggering is that it removes the problems of zeroes and ones catching associated with pulse triggered flipflops (eg. [[MasterFlip-slave flop_(technologyelectronics)#Master.E2.80.93slave_.28pulse-triggered.29_D_flip-flop|master slave]] flip flops]]).

{{DEFAULTSORT:Pulse Transition Detector}}