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In the issue stage, instructions are issued for execution if all operands and reservation stations are ready or else they are stalled. Registers are renamed in this step, eliminating WAR and WAW hazards.
*Retrieve the next instruction from the head of the instruction queue.
If the instruction operands are currently in the registers <!-- Unclear --> **If there is a matching empty reservation station (i.e., functional unit is available) then: issue the instruction
**Else, there is not a matching empty reservation station (i.e., functional unit is not available) then: stall the instruction until a station or buffer is free
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